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![Greg Kroah-Hartman](/assets/img/avatar_default.png)
Now that the SPDX tag is in all USB files, that identifies the license in a specific and legally-defined manner. So the extra GPL text wording can be removed as it is no longer needed at all. This is done on a quest to remove the 700+ different ways that files in the kernel describe the GPL license text. And there's unneeded stuff like the address (sometimes incorrect) for the FSF which is never needed. No copyright headers or other non-license-description text was removed. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Bin Liu <b-liu@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
642 lines
16 KiB
C
642 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/usb.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
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#include "musb_core.h"
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#include "tusb6010.h"
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#define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
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#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
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struct tusb_dma_data {
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s8 dmareq;
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struct dma_chan *chan;
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};
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struct tusb_omap_dma_ch {
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struct musb *musb;
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void __iomem *tbase;
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unsigned long phys_offset;
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int epnum;
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u8 tx;
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struct musb_hw_ep *hw_ep;
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struct tusb_dma_data *dma_data;
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struct tusb_omap_dma *tusb_dma;
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dma_addr_t dma_addr;
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u32 len;
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u16 packet_sz;
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u16 transfer_packet_sz;
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u32 transfer_len;
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u32 completed_len;
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};
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struct tusb_omap_dma {
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struct dma_controller controller;
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void __iomem *tbase;
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struct tusb_dma_data dma_pool[MAX_DMAREQ];
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unsigned multichannel:1;
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};
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/*
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* Allocate dmareq0 to the current channel unless it's already taken
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*/
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static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
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{
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u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
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if (reg != 0) {
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dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
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chdat->epnum, reg & 0xf);
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return -EAGAIN;
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}
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if (chdat->tx)
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reg = (1 << 4) | chdat->epnum;
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else
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reg = chdat->epnum;
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musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
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return 0;
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}
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static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
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{
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u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
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if ((reg & 0xf) != chdat->epnum) {
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printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
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chdat->epnum, reg & 0xf);
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return;
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}
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musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
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}
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/*
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* See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
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* musb_gadget.c.
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*/
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static void tusb_omap_dma_cb(void *data)
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{
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struct dma_channel *channel = (struct dma_channel *)data;
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
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struct musb *musb = chdat->musb;
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struct device *dev = musb->controller;
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struct musb_hw_ep *hw_ep = chdat->hw_ep;
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void __iomem *ep_conf = hw_ep->conf;
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void __iomem *mbase = musb->mregs;
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unsigned long remaining, flags, pio;
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spin_lock_irqsave(&musb->lock, flags);
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dev_dbg(musb->controller, "ep%i %s dma callback\n",
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chdat->epnum, chdat->tx ? "tx" : "rx");
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if (chdat->tx)
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remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
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else
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remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
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remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
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/* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
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if (unlikely(remaining > chdat->transfer_len)) {
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dev_dbg(musb->controller, "Corrupt %s XFR_SIZE: 0x%08lx\n",
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chdat->tx ? "tx" : "rx", remaining);
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remaining = 0;
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}
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channel->actual_len = chdat->transfer_len - remaining;
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pio = chdat->len - channel->actual_len;
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dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
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/* Transfer remaining 1 - 31 bytes */
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if (pio > 0 && pio < 32) {
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u8 *buf;
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dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
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buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
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if (chdat->tx) {
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dma_unmap_single(dev, chdat->dma_addr,
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chdat->transfer_len,
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DMA_TO_DEVICE);
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musb_write_fifo(hw_ep, pio, buf);
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} else {
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dma_unmap_single(dev, chdat->dma_addr,
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chdat->transfer_len,
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DMA_FROM_DEVICE);
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musb_read_fifo(hw_ep, pio, buf);
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}
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channel->actual_len += pio;
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}
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if (!tusb_dma->multichannel)
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tusb_omap_free_shared_dmareq(chdat);
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channel->status = MUSB_DMA_STATUS_FREE;
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musb_dma_completion(musb, chdat->epnum, chdat->tx);
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/* We must terminate short tx transfers manually by setting TXPKTRDY.
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* REVISIT: This same problem may occur with other MUSB dma as well.
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* Easy to test with g_ether by pinging the MUSB board with ping -s54.
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*/
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if ((chdat->transfer_len < chdat->packet_sz)
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|| (chdat->transfer_len % chdat->packet_sz != 0)) {
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u16 csr;
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if (chdat->tx) {
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dev_dbg(musb->controller, "terminating short tx packet\n");
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musb_ep_select(mbase, chdat->epnum);
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csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
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csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
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| MUSB_TXCSR_P_WZC_BITS;
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musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
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}
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}
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spin_unlock_irqrestore(&musb->lock, flags);
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}
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static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
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u8 rndis_mode, dma_addr_t dma_addr, u32 len)
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{
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
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struct musb *musb = chdat->musb;
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struct device *dev = musb->controller;
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struct musb_hw_ep *hw_ep = chdat->hw_ep;
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void __iomem *mbase = musb->mregs;
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void __iomem *ep_conf = hw_ep->conf;
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dma_addr_t fifo_addr = hw_ep->fifo_sync;
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u32 dma_remaining;
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u16 csr;
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u32 psize;
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struct tusb_dma_data *dma_data;
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struct dma_async_tx_descriptor *dma_desc;
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struct dma_slave_config dma_cfg;
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enum dma_transfer_direction dma_dir;
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u32 port_window;
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int ret;
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if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
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return false;
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/*
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* HW issue #10: Async dma will eventually corrupt the XFR_SIZE
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* register which will cause missed DMA interrupt. We could try to
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* use a timer for the callback, but it is unsafe as the XFR_SIZE
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* register is corrupt, and we won't know if the DMA worked.
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*/
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if (dma_addr & 0x2)
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return false;
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/*
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* Because of HW issue #10, it seems like mixing sync DMA and async
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* PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
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* using the channel for DMA.
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*/
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if (chdat->tx)
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dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
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else
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dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
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dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
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if (dma_remaining) {
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dev_dbg(musb->controller, "Busy %s dma, not using: %08x\n",
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chdat->tx ? "tx" : "rx", dma_remaining);
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return false;
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}
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chdat->transfer_len = len & ~0x1f;
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if (len < packet_sz)
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chdat->transfer_packet_sz = chdat->transfer_len;
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else
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chdat->transfer_packet_sz = packet_sz;
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dma_data = chdat->dma_data;
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if (!tusb_dma->multichannel) {
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if (tusb_omap_use_shared_dmareq(chdat) != 0) {
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dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
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return false;
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}
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if (dma_data->dmareq < 0) {
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/* REVISIT: This should get blocked earlier, happens
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* with MSC ErrorRecoveryTest
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*/
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WARN_ON(1);
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return false;
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}
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}
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chdat->packet_sz = packet_sz;
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chdat->len = len;
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channel->actual_len = 0;
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chdat->dma_addr = dma_addr;
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channel->status = MUSB_DMA_STATUS_BUSY;
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/* Since we're recycling dma areas, we need to clean or invalidate */
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if (chdat->tx) {
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dma_dir = DMA_MEM_TO_DEV;
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dma_map_single(dev, phys_to_virt(dma_addr), len,
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DMA_TO_DEVICE);
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} else {
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dma_dir = DMA_DEV_TO_MEM;
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dma_map_single(dev, phys_to_virt(dma_addr), len,
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DMA_FROM_DEVICE);
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}
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memset(&dma_cfg, 0, sizeof(dma_cfg));
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/* Use 16-bit transfer if dma_addr is not 32-bit aligned */
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if ((dma_addr & 0x3) == 0) {
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dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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port_window = 8;
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} else {
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dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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port_window = 16;
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fifo_addr = hw_ep->fifo_async;
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}
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dev_dbg(musb->controller,
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"ep%i %s dma: %pad len: %u(%u) packet_sz: %i(%i)\n",
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chdat->epnum, chdat->tx ? "tx" : "rx", &dma_addr,
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chdat->transfer_len, len, chdat->transfer_packet_sz, packet_sz);
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dma_cfg.src_addr = fifo_addr;
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dma_cfg.dst_addr = fifo_addr;
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dma_cfg.src_port_window_size = port_window;
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dma_cfg.src_maxburst = port_window;
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dma_cfg.dst_port_window_size = port_window;
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dma_cfg.dst_maxburst = port_window;
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ret = dmaengine_slave_config(dma_data->chan, &dma_cfg);
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if (ret) {
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dev_err(musb->controller, "DMA slave config failed: %d\n", ret);
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return false;
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}
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dma_desc = dmaengine_prep_slave_single(dma_data->chan, dma_addr,
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chdat->transfer_len, dma_dir,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!dma_desc) {
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dev_err(musb->controller, "DMA prep_slave_single failed\n");
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return false;
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}
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dma_desc->callback = tusb_omap_dma_cb;
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dma_desc->callback_param = channel;
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dmaengine_submit(dma_desc);
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dev_dbg(musb->controller,
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"ep%i %s using %i-bit %s dma from %pad to %pad\n",
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chdat->epnum, chdat->tx ? "tx" : "rx",
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dma_cfg.src_addr_width * 8,
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((dma_addr & 0x3) == 0) ? "sync" : "async",
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(dma_dir == DMA_MEM_TO_DEV) ? &dma_addr : &fifo_addr,
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(dma_dir == DMA_MEM_TO_DEV) ? &fifo_addr : &dma_addr);
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/*
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* Prepare MUSB for DMA transfer
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*/
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musb_ep_select(mbase, chdat->epnum);
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if (chdat->tx) {
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csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
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csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
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| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
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csr &= ~MUSB_TXCSR_P_UNDERRUN;
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musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
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} else {
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csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
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csr |= MUSB_RXCSR_DMAENAB;
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csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
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musb_writew(hw_ep->regs, MUSB_RXCSR,
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csr | MUSB_RXCSR_P_WZC_BITS);
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}
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/* Start DMA transfer */
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dma_async_issue_pending(dma_data->chan);
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if (chdat->tx) {
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/* Send transfer_packet_sz packets at a time */
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psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
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psize &= ~0x7ff;
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psize |= chdat->transfer_packet_sz;
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musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
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musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
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TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
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} else {
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/* Receive transfer_packet_sz packets at a time */
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psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
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psize &= ~(0x7ff << 16);
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psize |= (chdat->transfer_packet_sz << 16);
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musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
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musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
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TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
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}
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return true;
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}
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static int tusb_omap_dma_abort(struct dma_channel *channel)
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{
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struct tusb_omap_dma_ch *chdat = to_chdat(channel);
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if (chdat->dma_data)
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dmaengine_terminate_all(chdat->dma_data->chan);
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channel->status = MUSB_DMA_STATUS_FREE;
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return 0;
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}
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static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
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{
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u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
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int i, dmareq_nr = -1;
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for (i = 0; i < MAX_DMAREQ; i++) {
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int cur = (reg & (0xf << (i * 5))) >> (i * 5);
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if (cur == 0) {
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dmareq_nr = i;
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break;
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}
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}
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if (dmareq_nr == -1)
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return -EAGAIN;
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reg |= (chdat->epnum << (dmareq_nr * 5));
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if (chdat->tx)
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reg |= ((1 << 4) << (dmareq_nr * 5));
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musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
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chdat->dma_data = &chdat->tusb_dma->dma_pool[dmareq_nr];
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return 0;
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}
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static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
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{
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u32 reg;
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if (!chdat || !chdat->dma_data || chdat->dma_data->dmareq < 0)
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return;
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reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
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reg &= ~(0x1f << (chdat->dma_data->dmareq * 5));
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musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
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chdat->dma_data = NULL;
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}
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static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
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static struct dma_channel *
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tusb_omap_dma_allocate(struct dma_controller *c,
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struct musb_hw_ep *hw_ep,
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u8 tx)
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{
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int ret, i;
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struct tusb_omap_dma *tusb_dma;
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struct musb *musb;
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struct dma_channel *channel = NULL;
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struct tusb_omap_dma_ch *chdat = NULL;
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struct tusb_dma_data *dma_data = NULL;
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tusb_dma = container_of(c, struct tusb_omap_dma, controller);
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musb = tusb_dma->controller.musb;
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/* REVISIT: Why does dmareq5 not work? */
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if (hw_ep->epnum == 0) {
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dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
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return NULL;
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}
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for (i = 0; i < MAX_DMAREQ; i++) {
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struct dma_channel *ch = dma_channel_pool[i];
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if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
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ch->status = MUSB_DMA_STATUS_FREE;
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channel = ch;
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chdat = ch->private_data;
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|
break;
|
|
}
|
|
}
|
|
|
|
if (!channel)
|
|
return NULL;
|
|
|
|
chdat->musb = tusb_dma->controller.musb;
|
|
chdat->tbase = tusb_dma->tbase;
|
|
chdat->hw_ep = hw_ep;
|
|
chdat->epnum = hw_ep->epnum;
|
|
chdat->completed_len = 0;
|
|
chdat->tusb_dma = tusb_dma;
|
|
if (tx)
|
|
chdat->tx = 1;
|
|
else
|
|
chdat->tx = 0;
|
|
|
|
channel->max_len = 0x7fffffff;
|
|
channel->desired_mode = 0;
|
|
channel->actual_len = 0;
|
|
|
|
if (!chdat->dma_data) {
|
|
if (tusb_dma->multichannel) {
|
|
ret = tusb_omap_dma_allocate_dmareq(chdat);
|
|
if (ret != 0)
|
|
goto free_dmareq;
|
|
} else {
|
|
chdat->dma_data = &tusb_dma->dma_pool[0];
|
|
}
|
|
}
|
|
|
|
dma_data = chdat->dma_data;
|
|
|
|
dev_dbg(musb->controller, "ep%i %s dma: %s dmareq%i\n",
|
|
chdat->epnum,
|
|
chdat->tx ? "tx" : "rx",
|
|
tusb_dma->multichannel ? "shared" : "dedicated",
|
|
dma_data->dmareq);
|
|
|
|
return channel;
|
|
|
|
free_dmareq:
|
|
tusb_omap_dma_free_dmareq(chdat);
|
|
|
|
dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
|
|
channel->status = MUSB_DMA_STATUS_UNKNOWN;
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static void tusb_omap_dma_release(struct dma_channel *channel)
|
|
{
|
|
struct tusb_omap_dma_ch *chdat = to_chdat(channel);
|
|
struct musb *musb = chdat->musb;
|
|
|
|
dev_dbg(musb->controller, "Release for ep%i\n", chdat->epnum);
|
|
|
|
channel->status = MUSB_DMA_STATUS_UNKNOWN;
|
|
|
|
dmaengine_terminate_sync(chdat->dma_data->chan);
|
|
tusb_omap_dma_free_dmareq(chdat);
|
|
|
|
channel = NULL;
|
|
}
|
|
|
|
void tusb_dma_controller_destroy(struct dma_controller *c)
|
|
{
|
|
struct tusb_omap_dma *tusb_dma;
|
|
int i;
|
|
|
|
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
|
|
for (i = 0; i < MAX_DMAREQ; i++) {
|
|
struct dma_channel *ch = dma_channel_pool[i];
|
|
if (ch) {
|
|
kfree(ch->private_data);
|
|
kfree(ch);
|
|
}
|
|
|
|
/* Free up the DMA channels */
|
|
if (tusb_dma && tusb_dma->dma_pool[i].chan)
|
|
dma_release_channel(tusb_dma->dma_pool[i].chan);
|
|
}
|
|
|
|
kfree(tusb_dma);
|
|
}
|
|
EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy);
|
|
|
|
static int tusb_omap_allocate_dma_pool(struct tusb_omap_dma *tusb_dma)
|
|
{
|
|
struct musb *musb = tusb_dma->controller.musb;
|
|
int i;
|
|
int ret = 0;
|
|
|
|
for (i = 0; i < MAX_DMAREQ; i++) {
|
|
struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
|
|
|
|
/*
|
|
* Request DMA channels:
|
|
* - one channel in case of non multichannel mode
|
|
* - MAX_DMAREQ number of channels in multichannel mode
|
|
*/
|
|
if (i == 0 || tusb_dma->multichannel) {
|
|
char ch_name[8];
|
|
|
|
sprintf(ch_name, "dmareq%d", i);
|
|
dma_data->chan = dma_request_chan(musb->controller,
|
|
ch_name);
|
|
if (IS_ERR(dma_data->chan)) {
|
|
dev_err(musb->controller,
|
|
"Failed to request %s\n", ch_name);
|
|
ret = PTR_ERR(dma_data->chan);
|
|
goto dma_error;
|
|
}
|
|
|
|
dma_data->dmareq = i;
|
|
} else {
|
|
dma_data->dmareq = -1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
dma_error:
|
|
for (; i >= 0; i--) {
|
|
struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
|
|
|
|
if (dma_data->dmareq >= 0)
|
|
dma_release_channel(dma_data->chan);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
struct dma_controller *
|
|
tusb_dma_controller_create(struct musb *musb, void __iomem *base)
|
|
{
|
|
void __iomem *tbase = musb->ctrl_base;
|
|
struct tusb_omap_dma *tusb_dma;
|
|
int i;
|
|
|
|
/* REVISIT: Get dmareq lines used from board-*.c */
|
|
|
|
musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
|
|
musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
|
|
|
|
musb_writel(tbase, TUSB_DMA_REQ_CONF,
|
|
TUSB_DMA_REQ_CONF_BURST_SIZE(2)
|
|
| TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
|
|
| TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
|
|
|
|
tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
|
|
if (!tusb_dma)
|
|
goto out;
|
|
|
|
tusb_dma->controller.musb = musb;
|
|
tusb_dma->tbase = musb->ctrl_base;
|
|
|
|
tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
|
|
tusb_dma->controller.channel_release = tusb_omap_dma_release;
|
|
tusb_dma->controller.channel_program = tusb_omap_dma_program;
|
|
tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
|
|
|
|
if (musb->tusb_revision >= TUSB_REV_30)
|
|
tusb_dma->multichannel = 1;
|
|
|
|
for (i = 0; i < MAX_DMAREQ; i++) {
|
|
struct dma_channel *ch;
|
|
struct tusb_omap_dma_ch *chdat;
|
|
|
|
ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
|
|
if (!ch)
|
|
goto cleanup;
|
|
|
|
dma_channel_pool[i] = ch;
|
|
|
|
chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
|
|
if (!chdat)
|
|
goto cleanup;
|
|
|
|
ch->status = MUSB_DMA_STATUS_UNKNOWN;
|
|
ch->private_data = chdat;
|
|
}
|
|
|
|
if (tusb_omap_allocate_dma_pool(tusb_dma))
|
|
goto cleanup;
|
|
|
|
return &tusb_dma->controller;
|
|
|
|
cleanup:
|
|
musb_dma_controller_destroy(&tusb_dma->controller);
|
|
out:
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL_GPL(tusb_dma_controller_create);
|