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229e5bdcd3
If HEVC frame consists of multiple slices, segment address has to be known in order to properly decode it. Add segment address field to slice parameters. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
241 lines
8.9 KiB
C
241 lines
8.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* These are the HEVC state controls for use with stateless HEVC
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* codec drivers.
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*
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* It turns out that these structs are not stable yet and will undergo
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* more changes. So keep them private until they are stable and ready to
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* become part of the official public API.
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*/
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#ifndef _HEVC_CTRLS_H_
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#define _HEVC_CTRLS_H_
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#include <linux/videodev2.h>
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/* The pixel format isn't stable at the moment and will likely be renamed. */
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#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */
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#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008)
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#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009)
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#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010)
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#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012)
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#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015)
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#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016)
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/* enum v4l2_ctrl_type type values */
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#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120
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#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121
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#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122
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#define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124
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enum v4l2_mpeg_video_hevc_decode_mode {
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V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
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V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED,
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};
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enum v4l2_mpeg_video_hevc_start_code {
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V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
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V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B,
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};
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#define V4L2_HEVC_SLICE_TYPE_B 0
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#define V4L2_HEVC_SLICE_TYPE_P 1
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#define V4L2_HEVC_SLICE_TYPE_I 2
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#define V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE (1ULL << 0)
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#define V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED (1ULL << 1)
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#define V4L2_HEVC_SPS_FLAG_AMP_ENABLED (1ULL << 2)
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#define V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET (1ULL << 3)
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#define V4L2_HEVC_SPS_FLAG_PCM_ENABLED (1ULL << 4)
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#define V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED (1ULL << 5)
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#define V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT (1ULL << 6)
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#define V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED (1ULL << 7)
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#define V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED (1ULL << 8)
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/* The controls are not stable at the moment and will likely be reworked. */
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struct v4l2_ctrl_hevc_sps {
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
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__u16 pic_width_in_luma_samples;
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__u16 pic_height_in_luma_samples;
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__u8 bit_depth_luma_minus8;
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__u8 bit_depth_chroma_minus8;
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__u8 log2_max_pic_order_cnt_lsb_minus4;
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__u8 sps_max_dec_pic_buffering_minus1;
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__u8 sps_max_num_reorder_pics;
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__u8 sps_max_latency_increase_plus1;
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__u8 log2_min_luma_coding_block_size_minus3;
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__u8 log2_diff_max_min_luma_coding_block_size;
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__u8 log2_min_luma_transform_block_size_minus2;
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__u8 log2_diff_max_min_luma_transform_block_size;
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__u8 max_transform_hierarchy_depth_inter;
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__u8 max_transform_hierarchy_depth_intra;
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__u8 pcm_sample_bit_depth_luma_minus1;
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__u8 pcm_sample_bit_depth_chroma_minus1;
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__u8 log2_min_pcm_luma_coding_block_size_minus3;
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__u8 log2_diff_max_min_pcm_luma_coding_block_size;
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__u8 num_short_term_ref_pic_sets;
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__u8 num_long_term_ref_pics_sps;
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__u8 chroma_format_idc;
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__u8 sps_max_sub_layers_minus1;
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__u64 flags;
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};
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#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED (1ULL << 0)
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#define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT (1ULL << 1)
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#define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED (1ULL << 2)
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#define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT (1ULL << 3)
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#define V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED (1ULL << 4)
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#define V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED (1ULL << 5)
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#define V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED (1ULL << 6)
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#define V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT (1ULL << 7)
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#define V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED (1ULL << 8)
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#define V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED (1ULL << 9)
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#define V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED (1ULL << 10)
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#define V4L2_HEVC_PPS_FLAG_TILES_ENABLED (1ULL << 11)
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#define V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED (1ULL << 12)
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#define V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED (1ULL << 13)
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#define V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 14)
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#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED (1ULL << 15)
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#define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER (1ULL << 16)
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#define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT (1ULL << 17)
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#define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18)
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#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT (1ULL << 19)
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#define V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING (1ULL << 20)
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struct v4l2_ctrl_hevc_pps {
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
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__u8 num_extra_slice_header_bits;
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__u8 num_ref_idx_l0_default_active_minus1;
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__u8 num_ref_idx_l1_default_active_minus1;
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__s8 init_qp_minus26;
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__u8 diff_cu_qp_delta_depth;
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__s8 pps_cb_qp_offset;
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__s8 pps_cr_qp_offset;
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__u8 num_tile_columns_minus1;
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__u8 num_tile_rows_minus1;
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__u8 column_width_minus1[20];
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__u8 row_height_minus1[22];
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__s8 pps_beta_offset_div2;
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__s8 pps_tc_offset_div2;
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__u8 log2_parallel_merge_level_minus2;
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__u8 padding[4];
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__u64 flags;
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};
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#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01
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#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER 0x02
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#define V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR 0x03
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#define V4L2_HEVC_DPB_ENTRIES_NUM_MAX 16
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struct v4l2_hevc_dpb_entry {
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__u64 timestamp;
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__u8 rps;
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__u8 field_pic;
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__u16 pic_order_cnt[2];
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__u8 padding[2];
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};
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struct v4l2_hevc_pred_weight_table {
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__s8 delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__s8 luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__s8 delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
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__s8 chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
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__s8 delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__s8 luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__s8 delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
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__s8 chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2];
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__u8 padding[6];
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__u8 luma_log2_weight_denom;
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__s8 delta_chroma_log2_weight_denom;
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};
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA (1ULL << 0)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA (1ULL << 1)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED (1ULL << 2)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO (1ULL << 3)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT (1ULL << 4)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0 (1ULL << 5)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV (1ULL << 6)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8)
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#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 9)
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struct v4l2_ctrl_hevc_slice_params {
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__u32 bit_size;
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__u32 data_bit_offset;
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */
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__u8 nal_unit_type;
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__u8 nuh_temporal_id_plus1;
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
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__u8 slice_type;
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__u8 colour_plane_id;
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__u16 slice_pic_order_cnt;
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__u8 num_ref_idx_l0_active_minus1;
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__u8 num_ref_idx_l1_active_minus1;
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__u8 collocated_ref_idx;
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__u8 five_minus_max_num_merge_cand;
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__s8 slice_qp_delta;
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__s8 slice_cb_qp_offset;
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__s8 slice_cr_qp_offset;
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__s8 slice_act_y_qp_offset;
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__s8 slice_act_cb_qp_offset;
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__s8 slice_act_cr_qp_offset;
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__s8 slice_beta_offset_div2;
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__s8 slice_tc_offset_div2;
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */
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__u8 pic_struct;
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
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__u32 slice_segment_addr;
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__u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 padding;
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/* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */
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struct v4l2_hevc_pred_weight_table pred_weight_table;
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__u64 flags;
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};
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#define V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC 0x1
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#define V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC 0x2
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#define V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR 0x4
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struct v4l2_ctrl_hevc_decode_params {
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__s32 pic_order_cnt_val;
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__u8 num_active_dpb_entries;
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struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 num_poc_st_curr_before;
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__u8 num_poc_st_curr_after;
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__u8 num_poc_lt_curr;
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__u8 poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u8 poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
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__u64 flags;
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};
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/* MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */
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#define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200)
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/*
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* V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP -
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* the number of data (in bits) to skip in the
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* slice segment header.
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* If non-IDR, the bits to be skipped go from syntax element "pic_output_flag"
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* to before syntax element "slice_temporal_mvp_enabled_flag".
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* If IDR, the skipped bits are just "pic_output_flag"
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* (separate_colour_plane_flag is not supported).
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*/
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#define V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP (V4L2_CID_CODEC_HANTRO_BASE + 0)
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#endif
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