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![Dan Carpenter](/assets/img/avatar_default.png)
The call to kstrtoul() will corrupt memory on 64 bit systems because an int is 4 bytes and a long is 8. Also it's not a good idea to let users trigger a dev_err() because it just ends up flooding /var/log/messages so I removed the printk. Fixes: 2ddd2086ea9c ('mfd: add Intel Broxton Whiskey Cove PMIC driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
477 lines
12 KiB
C
477 lines
12 KiB
C
/*
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* MFD core driver for Intel Broxton Whiskey Cove PMIC
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*
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* Copyright (C) 2015 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/acpi.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel_bxtwc.h>
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#include <asm/intel_pmc_ipc.h>
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/* PMIC device registers */
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#define REG_ADDR_MASK 0xFF00
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#define REG_ADDR_SHIFT 8
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#define REG_OFFSET_MASK 0xFF
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/* Interrupt Status Registers */
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#define BXTWC_IRQLVL1 0x4E02
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#define BXTWC_PWRBTNIRQ 0x4E03
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#define BXTWC_THRM0IRQ 0x4E04
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#define BXTWC_THRM1IRQ 0x4E05
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#define BXTWC_THRM2IRQ 0x4E06
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#define BXTWC_BCUIRQ 0x4E07
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#define BXTWC_ADCIRQ 0x4E08
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#define BXTWC_CHGR0IRQ 0x4E09
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#define BXTWC_CHGR1IRQ 0x4E0A
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#define BXTWC_GPIOIRQ0 0x4E0B
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#define BXTWC_GPIOIRQ1 0x4E0C
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#define BXTWC_CRITIRQ 0x4E0D
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/* Interrupt MASK Registers */
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#define BXTWC_MIRQLVL1 0x4E0E
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#define BXTWC_MPWRTNIRQ 0x4E0F
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#define BXTWC_MTHRM0IRQ 0x4E12
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#define BXTWC_MTHRM1IRQ 0x4E13
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#define BXTWC_MTHRM2IRQ 0x4E14
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#define BXTWC_MBCUIRQ 0x4E15
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#define BXTWC_MADCIRQ 0x4E16
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#define BXTWC_MCHGR0IRQ 0x4E17
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#define BXTWC_MCHGR1IRQ 0x4E18
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#define BXTWC_MGPIO0IRQ 0x4E19
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#define BXTWC_MGPIO1IRQ 0x4E1A
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#define BXTWC_MCRITIRQ 0x4E1B
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/* Whiskey Cove PMIC share same ACPI ID between different platforms */
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#define BROXTON_PMIC_WC_HRV 4
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/* Manage in two IRQ chips since mask registers are not consecutive */
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enum bxtwc_irqs {
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/* Level 1 */
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BXTWC_PWRBTN_LVL1_IRQ = 0,
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BXTWC_TMU_LVL1_IRQ,
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BXTWC_THRM_LVL1_IRQ,
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BXTWC_BCU_LVL1_IRQ,
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BXTWC_ADC_LVL1_IRQ,
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BXTWC_CHGR_LVL1_IRQ,
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BXTWC_GPIO_LVL1_IRQ,
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BXTWC_CRIT_LVL1_IRQ,
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/* Level 2 */
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BXTWC_PWRBTN_IRQ,
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};
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enum bxtwc_irqs_level2 {
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/* Level 2 */
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BXTWC_THRM0_IRQ = 0,
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BXTWC_THRM1_IRQ,
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BXTWC_THRM2_IRQ,
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BXTWC_BCU_IRQ,
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BXTWC_ADC_IRQ,
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BXTWC_CHGR0_IRQ,
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BXTWC_CHGR1_IRQ,
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BXTWC_GPIO0_IRQ,
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BXTWC_GPIO1_IRQ,
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BXTWC_CRIT_IRQ,
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};
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static const struct regmap_irq bxtwc_regmap_irqs[] = {
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REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),
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REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),
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REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),
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REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),
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REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),
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REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),
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REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),
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REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),
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REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 1, 0x03),
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};
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static const struct regmap_irq bxtwc_regmap_irqs_level2[] = {
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REGMAP_IRQ_REG(BXTWC_THRM0_IRQ, 0, 0xff),
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REGMAP_IRQ_REG(BXTWC_THRM1_IRQ, 1, 0xbf),
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REGMAP_IRQ_REG(BXTWC_THRM2_IRQ, 2, 0xff),
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REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 3, 0x1f),
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REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 4, 0xff),
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REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 5, 0x1f),
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REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 6, 0x1f),
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REGMAP_IRQ_REG(BXTWC_GPIO0_IRQ, 7, 0xff),
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REGMAP_IRQ_REG(BXTWC_GPIO1_IRQ, 8, 0x3f),
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REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 9, 0x03),
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
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.name = "bxtwc_irq_chip",
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.status_base = BXTWC_IRQLVL1,
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.mask_base = BXTWC_MIRQLVL1,
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.irqs = bxtwc_regmap_irqs,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),
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.num_regs = 2,
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};
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static struct regmap_irq_chip bxtwc_regmap_irq_chip_level2 = {
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.name = "bxtwc_irq_chip_level2",
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.status_base = BXTWC_THRM0IRQ,
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.mask_base = BXTWC_MTHRM0IRQ,
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.irqs = bxtwc_regmap_irqs_level2,
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.num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_level2),
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.num_regs = 10,
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};
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static struct resource gpio_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_GPIO0_IRQ, "GPIO0"),
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DEFINE_RES_IRQ_NAMED(BXTWC_GPIO1_IRQ, "GPIO1"),
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};
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static struct resource adc_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),
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};
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static struct resource charger_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),
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DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),
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};
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static struct resource thermal_resources[] = {
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DEFINE_RES_IRQ(BXTWC_THRM0_IRQ),
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DEFINE_RES_IRQ(BXTWC_THRM1_IRQ),
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DEFINE_RES_IRQ(BXTWC_THRM2_IRQ),
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};
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static struct resource bcu_resources[] = {
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DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),
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};
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static struct mfd_cell bxt_wc_dev[] = {
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{
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.name = "bxt_wcove_gpadc",
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.num_resources = ARRAY_SIZE(adc_resources),
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.resources = adc_resources,
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},
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{
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.name = "bxt_wcove_thermal",
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.num_resources = ARRAY_SIZE(thermal_resources),
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.resources = thermal_resources,
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},
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{
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.name = "bxt_wcove_ext_charger",
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.num_resources = ARRAY_SIZE(charger_resources),
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.resources = charger_resources,
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},
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{
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.name = "bxt_wcove_bcu",
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.num_resources = ARRAY_SIZE(bcu_resources),
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.resources = bcu_resources,
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},
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{
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.name = "bxt_wcove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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{
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.name = "bxt_wcove_region",
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},
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};
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static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,
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unsigned int *val)
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{
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int ret;
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int i2c_addr;
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u8 ipc_in[2];
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u8 ipc_out[4];
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struct intel_soc_pmic *pmic = context;
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if (reg & REG_ADDR_MASK)
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i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
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else {
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i2c_addr = BXTWC_DEVICE1_ADDR;
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if (!i2c_addr) {
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dev_err(pmic->dev, "I2C address not set\n");
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return -EINVAL;
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}
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}
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reg &= REG_OFFSET_MASK;
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ipc_in[0] = reg;
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ipc_in[1] = i2c_addr;
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ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
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PMC_IPC_PMIC_ACCESS_READ,
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ipc_in, sizeof(ipc_in), (u32 *)ipc_out, 1);
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if (ret) {
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dev_err(pmic->dev, "Failed to read from PMIC\n");
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return ret;
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}
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*val = ipc_out[0];
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return 0;
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}
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static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,
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unsigned int val)
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{
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int ret;
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int i2c_addr;
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u8 ipc_in[3];
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struct intel_soc_pmic *pmic = context;
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if (reg & REG_ADDR_MASK)
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i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;
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else {
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i2c_addr = BXTWC_DEVICE1_ADDR;
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if (!i2c_addr) {
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dev_err(pmic->dev, "I2C address not set\n");
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return -EINVAL;
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}
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}
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reg &= REG_OFFSET_MASK;
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ipc_in[0] = reg;
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ipc_in[1] = i2c_addr;
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ipc_in[2] = val;
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ret = intel_pmc_ipc_command(PMC_IPC_PMIC_ACCESS,
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PMC_IPC_PMIC_ACCESS_WRITE,
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ipc_in, sizeof(ipc_in), NULL, 0);
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if (ret) {
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dev_err(pmic->dev, "Failed to write to PMIC\n");
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return ret;
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}
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return 0;
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}
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/* sysfs interfaces to r/w PMIC registers, required by initial script */
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static unsigned long bxtwc_reg_addr;
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static ssize_t bxtwc_reg_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sprintf(buf, "0x%lx\n", bxtwc_reg_addr);
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}
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static ssize_t bxtwc_reg_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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if (kstrtoul(buf, 0, &bxtwc_reg_addr)) {
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dev_err(dev, "Invalid register address\n");
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return -EINVAL;
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}
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return (ssize_t)count;
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}
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static ssize_t bxtwc_val_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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int ret;
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unsigned int val;
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
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if (ret < 0) {
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dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
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return -EIO;
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}
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return sprintf(buf, "0x%02x\n", val);
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}
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static ssize_t bxtwc_val_store(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t count)
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{
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int ret;
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unsigned int val;
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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ret = kstrtouint(buf, 0, &val);
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if (ret)
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return ret;
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ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);
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if (ret) {
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dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
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val, bxtwc_reg_addr);
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return -EIO;
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}
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return count;
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}
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static DEVICE_ATTR(addr, S_IWUSR | S_IRUSR, bxtwc_reg_show, bxtwc_reg_store);
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static DEVICE_ATTR(val, S_IWUSR | S_IRUSR, bxtwc_val_show, bxtwc_val_store);
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static struct attribute *bxtwc_attrs[] = {
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&dev_attr_addr.attr,
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&dev_attr_val.attr,
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NULL
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};
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static const struct attribute_group bxtwc_group = {
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.attrs = bxtwc_attrs,
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};
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static const struct regmap_config bxtwc_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.reg_write = regmap_ipc_byte_reg_write,
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.reg_read = regmap_ipc_byte_reg_read,
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};
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static int bxtwc_probe(struct platform_device *pdev)
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{
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int ret;
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acpi_handle handle;
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acpi_status status;
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unsigned long long hrv;
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struct intel_soc_pmic *pmic;
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handle = ACPI_HANDLE(&pdev->dev);
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status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv);
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if (ACPI_FAILURE(status)) {
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dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n");
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return -ENODEV;
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}
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if (hrv != BROXTON_PMIC_WC_HRV) {
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dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
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hrv);
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return -ENODEV;
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}
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pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
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if (!pmic)
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return -ENOMEM;
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ret = platform_get_irq(pdev, 0);
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if (ret < 0) {
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dev_err(&pdev->dev, "Invalid IRQ\n");
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return ret;
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}
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pmic->irq = ret;
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dev_set_drvdata(&pdev->dev, pmic);
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pmic->dev = &pdev->dev;
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pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic,
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&bxtwc_regmap_config);
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if (IS_ERR(pmic->regmap)) {
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ret = PTR_ERR(pmic->regmap);
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dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
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return ret;
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}
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ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
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IRQF_ONESHOT | IRQF_SHARED,
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0, &bxtwc_regmap_irq_chip,
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&pmic->irq_chip_data);
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if (ret) {
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dev_err(&pdev->dev, "Failed to add IRQ chip\n");
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return ret;
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}
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ret = regmap_add_irq_chip(pmic->regmap, pmic->irq,
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IRQF_ONESHOT | IRQF_SHARED,
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0, &bxtwc_regmap_irq_chip_level2,
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&pmic->irq_chip_data_level2);
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if (ret) {
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dev_err(&pdev->dev, "Failed to add secondary IRQ chip\n");
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goto err_irq_chip_level2;
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}
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ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
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ARRAY_SIZE(bxt_wc_dev), NULL, 0,
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NULL);
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if (ret) {
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dev_err(&pdev->dev, "Failed to add devices\n");
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goto err_mfd;
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}
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ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
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if (ret) {
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dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
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goto err_sysfs;
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}
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return 0;
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err_sysfs:
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mfd_remove_devices(&pdev->dev);
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err_mfd:
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regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
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err_irq_chip_level2:
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regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
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return ret;
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}
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static int bxtwc_remove(struct platform_device *pdev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
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sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
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mfd_remove_devices(&pdev->dev);
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regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data);
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regmap_del_irq_chip(pmic->irq, pmic->irq_chip_data_level2);
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return 0;
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}
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static void bxtwc_shutdown(struct platform_device *pdev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev);
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disable_irq(pmic->irq);
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}
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#ifdef CONFIG_PM_SLEEP
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static int bxtwc_suspend(struct device *dev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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disable_irq(pmic->irq);
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return 0;
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}
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static int bxtwc_resume(struct device *dev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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enable_irq(pmic->irq);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
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static const struct acpi_device_id bxtwc_acpi_ids[] = {
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{ "INT34D3", },
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{ }
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};
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MODULE_DEVICE_TABLE(acpi, pmic_acpi_ids);
|
|
|
|
static struct platform_driver bxtwc_driver = {
|
|
.probe = bxtwc_probe,
|
|
.remove = bxtwc_remove,
|
|
.shutdown = bxtwc_shutdown,
|
|
.driver = {
|
|
.name = "BXTWC PMIC",
|
|
.pm = &bxtwc_pm_ops,
|
|
.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(bxtwc_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>");
|