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![Thomas Gleixner](/assets/img/avatar_default.png)
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
334 lines
7.7 KiB
C
334 lines
7.7 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 SoC ADC driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* This driver synchronizes access to the JZ4740 ADC core between the
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* JZ4740 battery and hwmon drivers.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/clk.h>
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#include <linux/mfd/core.h>
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#include <linux/jz4740-adc.h>
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#define JZ_REG_ADC_ENABLE 0x00
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#define JZ_REG_ADC_CFG 0x04
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#define JZ_REG_ADC_CTRL 0x08
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#define JZ_REG_ADC_STATUS 0x0c
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#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10
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#define JZ_REG_ADC_BATTERY_BASE 0x1c
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#define JZ_REG_ADC_HWMON_BASE 0x20
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#define JZ_ADC_ENABLE_TOUCH BIT(2)
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#define JZ_ADC_ENABLE_BATTERY BIT(1)
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#define JZ_ADC_ENABLE_ADCIN BIT(0)
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enum {
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JZ_ADC_IRQ_ADCIN = 0,
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JZ_ADC_IRQ_BATTERY,
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JZ_ADC_IRQ_TOUCH,
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JZ_ADC_IRQ_PENUP,
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JZ_ADC_IRQ_PENDOWN,
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};
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struct jz4740_adc {
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struct resource *mem;
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void __iomem *base;
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int irq;
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struct irq_chip_generic *gc;
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struct clk *clk;
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atomic_t clk_ref;
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spinlock_t lock;
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};
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static void jz4740_adc_irq_demux(struct irq_desc *desc)
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{
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struct irq_chip_generic *gc = irq_desc_get_handler_data(desc);
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uint8_t status;
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unsigned int i;
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status = readb(gc->reg_base + JZ_REG_ADC_STATUS);
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for (i = 0; i < 5; ++i) {
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if (status & BIT(i))
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generic_handle_irq(gc->irq_base + i);
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}
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}
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/* Refcounting for the ADC clock is done in here instead of in the clock
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* framework, because it is the only clock which is shared between multiple
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* devices and thus is the only clock which needs refcounting */
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static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
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{
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if (atomic_inc_return(&adc->clk_ref) == 1)
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clk_prepare_enable(adc->clk);
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}
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static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
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{
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if (atomic_dec_return(&adc->clk_ref) == 0)
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clk_disable_unprepare(adc->clk);
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}
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static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
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bool enabled)
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{
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unsigned long flags;
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uint8_t val;
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spin_lock_irqsave(&adc->lock, flags);
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val = readb(adc->base + JZ_REG_ADC_ENABLE);
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if (enabled)
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val |= BIT(engine);
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else
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val &= ~BIT(engine);
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writeb(val, adc->base + JZ_REG_ADC_ENABLE);
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spin_unlock_irqrestore(&adc->lock, flags);
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}
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static int jz4740_adc_cell_enable(struct platform_device *pdev)
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{
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struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
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jz4740_adc_clk_enable(adc);
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jz4740_adc_set_enabled(adc, pdev->id, true);
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return 0;
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}
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static int jz4740_adc_cell_disable(struct platform_device *pdev)
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{
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struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
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jz4740_adc_set_enabled(adc, pdev->id, false);
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jz4740_adc_clk_disable(adc);
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return 0;
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}
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int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
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{
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struct jz4740_adc *adc = dev_get_drvdata(dev);
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unsigned long flags;
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uint32_t cfg;
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if (!adc)
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return -ENODEV;
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spin_lock_irqsave(&adc->lock, flags);
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cfg = readl(adc->base + JZ_REG_ADC_CFG);
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cfg &= ~mask;
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cfg |= val;
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writel(cfg, adc->base + JZ_REG_ADC_CFG);
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spin_unlock_irqrestore(&adc->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
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static struct resource jz4740_hwmon_resources[] = {
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{
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.start = JZ_ADC_IRQ_ADCIN,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = JZ_REG_ADC_HWMON_BASE,
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.end = JZ_REG_ADC_HWMON_BASE + 3,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource jz4740_battery_resources[] = {
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{
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.start = JZ_ADC_IRQ_BATTERY,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = JZ_REG_ADC_BATTERY_BASE,
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.end = JZ_REG_ADC_BATTERY_BASE + 3,
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.flags = IORESOURCE_MEM,
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},
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};
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static const struct mfd_cell jz4740_adc_cells[] = {
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{
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.id = 0,
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.name = "jz4740-hwmon",
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.num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
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.resources = jz4740_hwmon_resources,
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.enable = jz4740_adc_cell_enable,
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.disable = jz4740_adc_cell_disable,
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},
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{
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.id = 1,
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.name = "jz4740-battery",
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.num_resources = ARRAY_SIZE(jz4740_battery_resources),
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.resources = jz4740_battery_resources,
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.enable = jz4740_adc_cell_enable,
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.disable = jz4740_adc_cell_disable,
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},
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};
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static int jz4740_adc_probe(struct platform_device *pdev)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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struct jz4740_adc *adc;
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struct resource *mem_base;
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int ret;
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int irq_base;
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adc = devm_kzalloc(&pdev->dev, sizeof(*adc), GFP_KERNEL);
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if (!adc) {
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dev_err(&pdev->dev, "Failed to allocate driver structure\n");
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return -ENOMEM;
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}
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adc->irq = platform_get_irq(pdev, 0);
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if (adc->irq < 0) {
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ret = adc->irq;
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dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
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return ret;
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}
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irq_base = platform_get_irq(pdev, 1);
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if (irq_base < 0) {
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dev_err(&pdev->dev, "Failed to get irq base: %d\n", irq_base);
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return irq_base;
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}
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mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem_base) {
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dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
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return -ENOENT;
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}
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/* Only request the shared registers for the MFD driver */
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adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
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pdev->name);
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if (!adc->mem) {
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dev_err(&pdev->dev, "Failed to request mmio memory region\n");
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return -EBUSY;
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}
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adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
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if (!adc->base) {
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ret = -EBUSY;
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dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
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goto err_release_mem_region;
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}
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adc->clk = clk_get(&pdev->dev, "adc");
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if (IS_ERR(adc->clk)) {
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ret = PTR_ERR(adc->clk);
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dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
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goto err_iounmap;
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}
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spin_lock_init(&adc->lock);
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atomic_set(&adc->clk_ref, 0);
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platform_set_drvdata(pdev, adc);
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gc = irq_alloc_generic_chip("INTC", 1, irq_base, adc->base,
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handle_level_irq);
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ct = gc->chip_types;
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ct->regs.mask = JZ_REG_ADC_CTRL;
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ct->regs.ack = JZ_REG_ADC_STATUS;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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irq_setup_generic_chip(gc, IRQ_MSK(5), IRQ_GC_INIT_MASK_CACHE, 0,
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IRQ_NOPROBE | IRQ_LEVEL);
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adc->gc = gc;
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irq_set_chained_handler_and_data(adc->irq, jz4740_adc_irq_demux, gc);
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writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
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writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
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ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
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ARRAY_SIZE(jz4740_adc_cells), mem_base,
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irq_base, NULL);
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if (ret < 0)
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goto err_clk_put;
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return 0;
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err_clk_put:
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clk_put(adc->clk);
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err_iounmap:
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iounmap(adc->base);
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err_release_mem_region:
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release_mem_region(adc->mem->start, resource_size(adc->mem));
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return ret;
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}
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static int jz4740_adc_remove(struct platform_device *pdev)
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{
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struct jz4740_adc *adc = platform_get_drvdata(pdev);
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mfd_remove_devices(&pdev->dev);
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irq_remove_generic_chip(adc->gc, IRQ_MSK(5), IRQ_NOPROBE | IRQ_LEVEL, 0);
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kfree(adc->gc);
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irq_set_chained_handler_and_data(adc->irq, NULL, NULL);
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iounmap(adc->base);
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release_mem_region(adc->mem->start, resource_size(adc->mem));
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clk_put(adc->clk);
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return 0;
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}
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static struct platform_driver jz4740_adc_driver = {
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.probe = jz4740_adc_probe,
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.remove = jz4740_adc_remove,
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.driver = {
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.name = "jz4740-adc",
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},
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};
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module_platform_driver(jz4740_adc_driver);
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MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
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MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:jz4740-adc");
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