Swapnil Jakhade fa10517211 phy: cadence: Sierra: Add PHY PCS common register configurations ... Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-8-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2021-12-27 16:35:09 +05:30
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cdns-dphy.c	phy: cadence: convert to devm_platform_ioremap_resource	2020-11-16 12:47:46 +05:30
Kconfig	phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)	2021-03-31 16:43:21 +05:30
Makefile	phy: cadence: salvo: add salvo phy driver	2020-05-07 09:46:36 +05:30
phy-cadence-salvo.c	phy: cadence: convert to devm_platform_ioremap_resource	2020-11-16 12:47:46 +05:30
phy-cadence-sierra.c	phy: cadence: Sierra: Add PHY PCS common register configurations	2021-12-27 16:35:09 +05:30
phy-cadence-torrent.c	phy: cadence-torrent: use swap() to make code cleaner	2021-11-23 11:24:30 +05:30