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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-29 20:30:35 +00:00
![Gustavo A. R. Silva](/assets/img/avatar_default.png)
The current codebase makes use of the zero-length array language
extension to the C90 standard, but the preferred mechanism to declare
variable-length types such as these ones is a flexible array member[1][2],
introduced in C99:
struct foo {
int stuff;
struct boo array[];
};
By making use of the mechanism above, we will get a compiler warning
in case the flexible array does not occur last in the structure, which
will help us prevent some kind of undefined behavior bugs from being
inadvertently introduced[3] to the codebase from now on.
Also, notice that, dynamic memory allocations won't be affected by
this change:
"Flexible array members have incomplete type, and so the sizeof operator
may not be applied. As a quirk of the original implementation of
zero-length arrays, sizeof evaluates to zero."[1]
This issue was found with the help of Coccinelle.
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
[2] https://github.com/KSPP/linux/issues/21
[3] commit 7649773293
("cxgb3/l2t: Fix undefined behaviour")
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Link: https://lore.kernel.org/r/20200213003535.GA3269@embeddedor.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
501 lines
13 KiB
C
501 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2018 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "virt-dma.h"
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/* registers common for all channels */
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#define UNIPHIER_MDMAC_CMD 0x000 /* issue DMA start/abort */
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#define UNIPHIER_MDMAC_CMD_ABORT BIT(31) /* 1: abort, 0: start */
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/* per-channel registers */
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#define UNIPHIER_MDMAC_CH_OFFSET 0x100
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#define UNIPHIER_MDMAC_CH_STRIDE 0x040
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#define UNIPHIER_MDMAC_CH_IRQ_STAT 0x010 /* current hw status (RO) */
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#define UNIPHIER_MDMAC_CH_IRQ_REQ 0x014 /* latched STAT (WOC) */
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#define UNIPHIER_MDMAC_CH_IRQ_EN 0x018 /* IRQ enable mask */
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#define UNIPHIER_MDMAC_CH_IRQ_DET 0x01c /* REQ & EN (RO) */
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#define UNIPHIER_MDMAC_CH_IRQ__ABORT BIT(13)
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#define UNIPHIER_MDMAC_CH_IRQ__DONE BIT(1)
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#define UNIPHIER_MDMAC_CH_SRC_MODE 0x020 /* mode of source */
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#define UNIPHIER_MDMAC_CH_DEST_MODE 0x024 /* mode of destination */
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#define UNIPHIER_MDMAC_CH_MODE__ADDR_INC (0 << 4)
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#define UNIPHIER_MDMAC_CH_MODE__ADDR_DEC (1 << 4)
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#define UNIPHIER_MDMAC_CH_MODE__ADDR_FIXED (2 << 4)
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#define UNIPHIER_MDMAC_CH_SRC_ADDR 0x028 /* source address */
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#define UNIPHIER_MDMAC_CH_DEST_ADDR 0x02c /* destination address */
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#define UNIPHIER_MDMAC_CH_SIZE 0x030 /* transfer bytes */
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#define UNIPHIER_MDMAC_SLAVE_BUSWIDTHS \
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(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
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struct uniphier_mdmac_desc {
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struct virt_dma_desc vd;
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struct scatterlist *sgl;
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unsigned int sg_len;
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unsigned int sg_cur;
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enum dma_transfer_direction dir;
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};
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struct uniphier_mdmac_chan {
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struct virt_dma_chan vc;
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struct uniphier_mdmac_device *mdev;
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struct uniphier_mdmac_desc *md;
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void __iomem *reg_ch_base;
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unsigned int chan_id;
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};
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struct uniphier_mdmac_device {
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struct dma_device ddev;
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struct clk *clk;
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void __iomem *reg_base;
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struct uniphier_mdmac_chan channels[];
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};
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static struct uniphier_mdmac_chan *
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to_uniphier_mdmac_chan(struct virt_dma_chan *vc)
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{
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return container_of(vc, struct uniphier_mdmac_chan, vc);
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}
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static struct uniphier_mdmac_desc *
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to_uniphier_mdmac_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct uniphier_mdmac_desc, vd);
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}
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/* mc->vc.lock must be held by caller */
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static struct uniphier_mdmac_desc *
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uniphier_mdmac_next_desc(struct uniphier_mdmac_chan *mc)
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{
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struct virt_dma_desc *vd;
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vd = vchan_next_desc(&mc->vc);
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if (!vd) {
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mc->md = NULL;
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return NULL;
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}
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list_del(&vd->node);
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mc->md = to_uniphier_mdmac_desc(vd);
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return mc->md;
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}
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/* mc->vc.lock must be held by caller */
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static void uniphier_mdmac_handle(struct uniphier_mdmac_chan *mc,
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struct uniphier_mdmac_desc *md)
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{
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struct uniphier_mdmac_device *mdev = mc->mdev;
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struct scatterlist *sg;
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u32 irq_flag = UNIPHIER_MDMAC_CH_IRQ__DONE;
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u32 src_mode, src_addr, dest_mode, dest_addr, chunk_size;
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sg = &md->sgl[md->sg_cur];
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if (md->dir == DMA_MEM_TO_DEV) {
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src_mode = UNIPHIER_MDMAC_CH_MODE__ADDR_INC;
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src_addr = sg_dma_address(sg);
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dest_mode = UNIPHIER_MDMAC_CH_MODE__ADDR_FIXED;
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dest_addr = 0;
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} else {
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src_mode = UNIPHIER_MDMAC_CH_MODE__ADDR_FIXED;
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src_addr = 0;
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dest_mode = UNIPHIER_MDMAC_CH_MODE__ADDR_INC;
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dest_addr = sg_dma_address(sg);
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}
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chunk_size = sg_dma_len(sg);
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writel(src_mode, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SRC_MODE);
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writel(dest_mode, mc->reg_ch_base + UNIPHIER_MDMAC_CH_DEST_MODE);
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writel(src_addr, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SRC_ADDR);
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writel(dest_addr, mc->reg_ch_base + UNIPHIER_MDMAC_CH_DEST_ADDR);
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writel(chunk_size, mc->reg_ch_base + UNIPHIER_MDMAC_CH_SIZE);
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/* write 1 to clear */
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writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ);
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writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_EN);
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writel(BIT(mc->chan_id), mdev->reg_base + UNIPHIER_MDMAC_CMD);
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}
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/* mc->vc.lock must be held by caller */
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static void uniphier_mdmac_start(struct uniphier_mdmac_chan *mc)
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{
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struct uniphier_mdmac_desc *md;
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md = uniphier_mdmac_next_desc(mc);
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if (md)
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uniphier_mdmac_handle(mc, md);
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}
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/* mc->vc.lock must be held by caller */
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static int uniphier_mdmac_abort(struct uniphier_mdmac_chan *mc)
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{
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struct uniphier_mdmac_device *mdev = mc->mdev;
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u32 irq_flag = UNIPHIER_MDMAC_CH_IRQ__ABORT;
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u32 val;
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/* write 1 to clear */
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writel(irq_flag, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ);
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writel(UNIPHIER_MDMAC_CMD_ABORT | BIT(mc->chan_id),
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mdev->reg_base + UNIPHIER_MDMAC_CMD);
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/*
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* Abort should be accepted soon. We poll the bit here instead of
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* waiting for the interrupt.
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*/
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return readl_poll_timeout(mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ,
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val, val & irq_flag, 0, 20);
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}
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static irqreturn_t uniphier_mdmac_interrupt(int irq, void *dev_id)
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{
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struct uniphier_mdmac_chan *mc = dev_id;
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struct uniphier_mdmac_desc *md;
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irqreturn_t ret = IRQ_HANDLED;
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u32 irq_stat;
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spin_lock(&mc->vc.lock);
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irq_stat = readl(mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_DET);
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/*
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* Some channels share a single interrupt line. If the IRQ status is 0,
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* this is probably triggered by a different channel.
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*/
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if (!irq_stat) {
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ret = IRQ_NONE;
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goto out;
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}
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/* write 1 to clear */
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writel(irq_stat, mc->reg_ch_base + UNIPHIER_MDMAC_CH_IRQ_REQ);
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/*
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* UNIPHIER_MDMAC_CH_IRQ__DONE interrupt is asserted even when the DMA
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* is aborted. To distinguish the normal completion and the abort,
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* check mc->md. If it is NULL, we are aborting.
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*/
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md = mc->md;
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if (!md)
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goto out;
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md->sg_cur++;
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if (md->sg_cur >= md->sg_len) {
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vchan_cookie_complete(&md->vd);
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md = uniphier_mdmac_next_desc(mc);
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if (!md)
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goto out;
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}
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uniphier_mdmac_handle(mc, md);
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out:
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spin_unlock(&mc->vc.lock);
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return ret;
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}
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static void uniphier_mdmac_free_chan_resources(struct dma_chan *chan)
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{
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vchan_free_chan_resources(to_virt_chan(chan));
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}
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static struct dma_async_tx_descriptor *
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uniphier_mdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len,
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enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct uniphier_mdmac_desc *md;
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if (!is_slave_direction(direction))
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return NULL;
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md = kzalloc(sizeof(*md), GFP_NOWAIT);
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if (!md)
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return NULL;
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md->sgl = sgl;
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md->sg_len = sg_len;
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md->dir = direction;
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return vchan_tx_prep(vc, &md->vd, flags);
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}
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static int uniphier_mdmac_terminate_all(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct uniphier_mdmac_chan *mc = to_uniphier_mdmac_chan(vc);
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unsigned long flags;
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int ret = 0;
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LIST_HEAD(head);
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spin_lock_irqsave(&vc->lock, flags);
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if (mc->md) {
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vchan_terminate_vdesc(&mc->md->vd);
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mc->md = NULL;
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ret = uniphier_mdmac_abort(mc);
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}
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vchan_get_all_descriptors(vc, &head);
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spin_unlock_irqrestore(&vc->lock, flags);
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vchan_dma_desc_free_list(vc, &head);
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return ret;
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}
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static void uniphier_mdmac_synchronize(struct dma_chan *chan)
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{
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vchan_synchronize(to_virt_chan(chan));
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}
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static enum dma_status uniphier_mdmac_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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{
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struct virt_dma_chan *vc;
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struct virt_dma_desc *vd;
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struct uniphier_mdmac_chan *mc;
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struct uniphier_mdmac_desc *md = NULL;
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enum dma_status stat;
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unsigned long flags;
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int i;
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stat = dma_cookie_status(chan, cookie, txstate);
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/* Return immediately if we do not need to compute the residue. */
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if (stat == DMA_COMPLETE || !txstate)
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return stat;
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vc = to_virt_chan(chan);
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spin_lock_irqsave(&vc->lock, flags);
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mc = to_uniphier_mdmac_chan(vc);
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if (mc->md && mc->md->vd.tx.cookie == cookie) {
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/* residue from the on-flight chunk */
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txstate->residue = readl(mc->reg_ch_base +
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UNIPHIER_MDMAC_CH_SIZE);
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md = mc->md;
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}
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if (!md) {
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vd = vchan_find_desc(vc, cookie);
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if (vd)
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md = to_uniphier_mdmac_desc(vd);
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}
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if (md) {
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/* residue from the queued chunks */
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for (i = md->sg_cur; i < md->sg_len; i++)
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txstate->residue += sg_dma_len(&md->sgl[i]);
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}
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spin_unlock_irqrestore(&vc->lock, flags);
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return stat;
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}
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static void uniphier_mdmac_issue_pending(struct dma_chan *chan)
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{
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struct virt_dma_chan *vc = to_virt_chan(chan);
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struct uniphier_mdmac_chan *mc = to_uniphier_mdmac_chan(vc);
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unsigned long flags;
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spin_lock_irqsave(&vc->lock, flags);
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if (vchan_issue_pending(vc) && !mc->md)
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uniphier_mdmac_start(mc);
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spin_unlock_irqrestore(&vc->lock, flags);
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}
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static void uniphier_mdmac_desc_free(struct virt_dma_desc *vd)
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{
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kfree(to_uniphier_mdmac_desc(vd));
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}
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static int uniphier_mdmac_chan_init(struct platform_device *pdev,
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struct uniphier_mdmac_device *mdev,
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int chan_id)
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{
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struct device *dev = &pdev->dev;
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struct uniphier_mdmac_chan *mc = &mdev->channels[chan_id];
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char *irq_name;
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int irq, ret;
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irq = platform_get_irq(pdev, chan_id);
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if (irq < 0)
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return irq;
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irq_name = devm_kasprintf(dev, GFP_KERNEL, "uniphier-mio-dmac-ch%d",
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chan_id);
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if (!irq_name)
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return -ENOMEM;
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ret = devm_request_irq(dev, irq, uniphier_mdmac_interrupt,
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IRQF_SHARED, irq_name, mc);
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if (ret)
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return ret;
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mc->mdev = mdev;
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mc->reg_ch_base = mdev->reg_base + UNIPHIER_MDMAC_CH_OFFSET +
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UNIPHIER_MDMAC_CH_STRIDE * chan_id;
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mc->chan_id = chan_id;
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mc->vc.desc_free = uniphier_mdmac_desc_free;
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vchan_init(&mc->vc, &mdev->ddev);
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return 0;
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}
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static int uniphier_mdmac_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct uniphier_mdmac_device *mdev;
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struct dma_device *ddev;
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int nr_chans, ret, i;
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nr_chans = platform_irq_count(pdev);
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if (nr_chans < 0)
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return nr_chans;
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ret = dma_set_mask(dev, DMA_BIT_MASK(32));
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if (ret)
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return ret;
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mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
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GFP_KERNEL);
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if (!mdev)
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return -ENOMEM;
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mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mdev->reg_base))
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return PTR_ERR(mdev->reg_base);
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mdev->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(mdev->clk)) {
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dev_err(dev, "failed to get clock\n");
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return PTR_ERR(mdev->clk);
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}
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ret = clk_prepare_enable(mdev->clk);
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if (ret)
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return ret;
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ddev = &mdev->ddev;
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ddev->dev = dev;
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dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
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ddev->src_addr_widths = UNIPHIER_MDMAC_SLAVE_BUSWIDTHS;
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ddev->dst_addr_widths = UNIPHIER_MDMAC_SLAVE_BUSWIDTHS;
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ddev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
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ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
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ddev->device_free_chan_resources = uniphier_mdmac_free_chan_resources;
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ddev->device_prep_slave_sg = uniphier_mdmac_prep_slave_sg;
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ddev->device_terminate_all = uniphier_mdmac_terminate_all;
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ddev->device_synchronize = uniphier_mdmac_synchronize;
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ddev->device_tx_status = uniphier_mdmac_tx_status;
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ddev->device_issue_pending = uniphier_mdmac_issue_pending;
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INIT_LIST_HEAD(&ddev->channels);
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for (i = 0; i < nr_chans; i++) {
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ret = uniphier_mdmac_chan_init(pdev, mdev, i);
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if (ret)
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goto disable_clk;
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}
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ret = dma_async_device_register(ddev);
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if (ret)
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goto disable_clk;
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ret = of_dma_controller_register(dev->of_node, of_dma_xlate_by_chan_id,
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ddev);
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if (ret)
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goto unregister_dmac;
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platform_set_drvdata(pdev, mdev);
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return 0;
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unregister_dmac:
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dma_async_device_unregister(ddev);
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disable_clk:
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clk_disable_unprepare(mdev->clk);
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return ret;
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}
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static int uniphier_mdmac_remove(struct platform_device *pdev)
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{
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|
struct uniphier_mdmac_device *mdev = platform_get_drvdata(pdev);
|
|
struct dma_chan *chan;
|
|
int ret;
|
|
|
|
/*
|
|
* Before reaching here, almost all descriptors have been freed by the
|
|
* ->device_free_chan_resources() hook. However, each channel might
|
|
* be still holding one descriptor that was on-flight at that moment.
|
|
* Terminate it to make sure this hardware is no longer running. Then,
|
|
* free the channel resources once again to avoid memory leak.
|
|
*/
|
|
list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
|
|
ret = dmaengine_terminate_sync(chan);
|
|
if (ret)
|
|
return ret;
|
|
uniphier_mdmac_free_chan_resources(chan);
|
|
}
|
|
|
|
of_dma_controller_free(pdev->dev.of_node);
|
|
dma_async_device_unregister(&mdev->ddev);
|
|
clk_disable_unprepare(mdev->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id uniphier_mdmac_match[] = {
|
|
{ .compatible = "socionext,uniphier-mio-dmac" },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, uniphier_mdmac_match);
|
|
|
|
static struct platform_driver uniphier_mdmac_driver = {
|
|
.probe = uniphier_mdmac_probe,
|
|
.remove = uniphier_mdmac_remove,
|
|
.driver = {
|
|
.name = "uniphier-mio-dmac",
|
|
.of_match_table = uniphier_mdmac_match,
|
|
},
|
|
};
|
|
module_platform_driver(uniphier_mdmac_driver);
|
|
|
|
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
|
MODULE_DESCRIPTION("UniPhier MIO DMAC driver");
|
|
MODULE_LICENSE("GPL v2");
|