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829ec6408d
The SPI NOR controllers drivers must not be able to use structures that are meant just for the SPI NOR core. struct spi_nor_flash_parameter is filled at run-time with info gathered from flash_info, manufacturer and sfdp data. struct spi_nor_flash_parameter should be opaque to the SPI NOR controller drivers, make sure it is. spi_nor_option_flags, spi_nor_read_command, spi_nor_pp_command, spi_nor_read_command_index and spi_nor_pp_command_index are defined for the core use, make sure they are opaque to the SPI NOR controller drivers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
59 lines
2.1 KiB
C
59 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static void gd25q256_default_init(struct spi_nor *nor)
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{
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/*
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* Some manufacturer like GigaDevice may use different
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* bit to set QE on different memories, so the MFR can't
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* indicate the quad_enable method for this case, we need
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* to set it in the default_init fixup hook.
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*/
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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}
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static struct spi_nor_fixups gd25q256_fixups = {
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.default_init = gd25q256_default_init,
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};
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static const struct flash_info gigadevice_parts[] = {
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{ "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
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SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
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.fixups = &gd25q256_fixups },
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};
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const struct spi_nor_manufacturer spi_nor_gigadevice = {
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.name = "gigadevice",
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.parts = gigadevice_parts,
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.nparts = ARRAY_SIZE(gigadevice_parts),
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};
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