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829ec6408d
The SPI NOR controllers drivers must not be able to use structures that are meant just for the SPI NOR core. struct spi_nor_flash_parameter is filled at run-time with info gathered from flash_info, manufacturer and sfdp data. struct spi_nor_flash_parameter should be opaque to the SPI NOR controller drivers, make sure it is. spi_nor_option_flags, spi_nor_read_command, spi_nor_pp_command, spi_nor_read_command_index and spi_nor_pp_command_index are defined for the core use, make sure they are opaque to the SPI NOR controller drivers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
94 lines
2.7 KiB
C
94 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static const struct flash_info xilinx_parts[] = {
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/* Xilinx S3AN Internal Flash */
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{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
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{ "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
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{ "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
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{ "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
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{ "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
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};
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/*
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* This code converts an address to the Default Address Mode, that has non
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* power of two page sizes. We must support this mode because it is the default
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* mode supported by Xilinx tools, it can access the whole flash area and
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* changing over to the Power-of-two mode is irreversible and corrupts the
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* original data.
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* Addr can safely be unsigned int, the biggest S3AN device is smaller than
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* 4 MiB.
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*/
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static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
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{
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u32 offset, page;
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offset = addr % nor->page_size;
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page = addr / nor->page_size;
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page <<= (nor->page_size > 512) ? 10 : 9;
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return page | offset;
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}
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static int xilinx_nor_setup(struct spi_nor *nor,
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const struct spi_nor_hwcaps *hwcaps)
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{
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int ret;
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ret = spi_nor_xread_sr(nor, nor->bouncebuf);
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if (ret)
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return ret;
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nor->erase_opcode = SPINOR_OP_XSE;
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nor->program_opcode = SPINOR_OP_XPP;
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nor->read_opcode = SPINOR_OP_READ;
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nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
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/*
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* This flashes have a page size of 264 or 528 bytes (known as
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* Default addressing mode). It can be changed to a more standard
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* Power of two mode where the page size is 256/512. This comes
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* with a price: there is 3% less of space, the data is corrupted
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* and the page size cannot be changed back to default addressing
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* mode.
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*
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* The current addressing mode can be read from the XRDSR register
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* and should not be changed, because is a destructive operation.
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*/
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if (nor->bouncebuf[0] & XSR_PAGESIZE) {
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/* Flash in Power of 2 mode */
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nor->page_size = (nor->page_size == 264) ? 256 : 512;
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nor->mtd.writebufsize = nor->page_size;
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nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors;
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nor->mtd.erasesize = 8 * nor->page_size;
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} else {
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/* Flash in Default addressing mode */
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nor->params->convert_addr = s3an_convert_addr;
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nor->mtd.erasesize = nor->info->sector_size;
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}
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return 0;
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}
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static void xilinx_post_sfdp_fixups(struct spi_nor *nor)
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{
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nor->params->setup = xilinx_nor_setup;
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}
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static const struct spi_nor_fixups xilinx_fixups = {
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.post_sfdp = xilinx_post_sfdp_fixups,
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};
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const struct spi_nor_manufacturer spi_nor_xilinx = {
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.name = "xilinx",
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.parts = xilinx_parts,
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.nparts = ARRAY_SIZE(xilinx_parts),
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.fixups = &xilinx_fixups,
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};
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