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f414854c88
Apart from the infracfg block, the SMI block is used to enable the bus protection for some power domains. Add support for this block. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20201030113622.201188-7-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
94 lines
2.7 KiB
C
94 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8173_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8173_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mt8173-power.h>
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/*
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* MT8173 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
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[MT8173_POWER_DOMAIN_VDEC] = {
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.sta_mask = PWR_STATUS_VDEC,
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.ctl_offs = SPM_VDE_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8173_POWER_DOMAIN_VENC] = {
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.sta_mask = PWR_STATUS_VENC,
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.ctl_offs = SPM_VEN_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8173_POWER_DOMAIN_ISP] = {
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = SPM_ISP_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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},
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[MT8173_POWER_DOMAIN_MM] = {
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = SPM_DIS_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
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MT8173_TOP_AXI_PROT_EN_MM_M1),
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},
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},
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[MT8173_POWER_DOMAIN_VENC_LT] = {
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.sta_mask = PWR_STATUS_VENC_LT,
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.ctl_offs = SPM_VEN2_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8173_POWER_DOMAIN_AUDIO] = {
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.sta_mask = PWR_STATUS_AUDIO,
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.ctl_offs = SPM_AUDIO_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8173_POWER_DOMAIN_USB] = {
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.sta_mask = PWR_STATUS_USB,
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.ctl_offs = SPM_USB_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.caps = MTK_SCPD_ACTIVE_WAKEUP,
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},
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[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
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.sta_mask = PWR_STATUS_MFG_ASYNC,
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.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = 0,
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},
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[MT8173_POWER_DOMAIN_MFG_2D] = {
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.sta_mask = PWR_STATUS_MFG_2D,
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.ctl_offs = SPM_MFG_2D_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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},
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[MT8173_POWER_DOMAIN_MFG] = {
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = SPM_MFG_PWR_CON,
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.sram_pdn_bits = GENMASK(13, 8),
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.sram_pdn_ack_bits = GENMASK(21, 16),
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.bp_infracfg = {
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BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
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MT8173_TOP_AXI_PROT_EN_MFG_M0 |
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MT8173_TOP_AXI_PROT_EN_MFG_M1 |
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MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
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},
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},
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};
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static const struct scpsys_soc_data mt8173_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8173,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
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.pwr_sta_offs = SPM_PWR_STATUS,
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.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
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};
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#endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */
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