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fade9c2c6e
Although naming across the codebase isn't that consistent, it tends to follow certain patterns. Moreover, the term "flush" isn't defined in the Arm Architecture reference manual, and might be interpreted to mean clean, invalidate, or both for a cache. Rename arm64-internal functions to make the naming internally consistent, as well as making it consistent with the Arm ARM, by specifying whether it applies to the instruction, data, or both caches, whether the operation is a clean, invalidate, or both. Also specify which point the operation applies to, i.e., to the point of unification (PoU), coherency (PoC), or persistence (PoP). This commit applies the following sed transformation to all files under arch/arm64: "s/\b__flush_cache_range\b/caches_clean_inval_pou_macro/g;"\ "s/\b__flush_icache_range\b/caches_clean_inval_pou/g;"\ "s/\binvalidate_icache_range\b/icache_inval_pou/g;"\ "s/\b__flush_dcache_area\b/dcache_clean_inval_poc/g;"\ "s/\b__inval_dcache_area\b/dcache_inval_poc/g;"\ "s/__clean_dcache_area_poc\b/dcache_clean_poc/g;"\ "s/\b__clean_dcache_area_pop\b/dcache_clean_pop/g;"\ "s/\b__clean_dcache_area_pou\b/dcache_clean_pou/g;"\ "s/\b__flush_cache_user_range\b/caches_clean_inval_user_pou/g;"\ "s/\b__flush_icache_all\b/icache_inval_all_pou/g;" Note that __clean_dcache_area_poc is deliberately missing a word boundary check at the beginning in order to match the efistub symbols in image-vars.h. Also note that, despite its name, __flush_icache_range operates on both instruction and data caches. The name change here reflects that. No functional change intended. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Fuad Tabba <tabba@google.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20210524083001.2586635-19-tabba@google.com Signed-off-by: Will Deacon <will@kernel.org>
69 lines
1.5 KiB
ArmAsm
69 lines
1.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* EFI entry point.
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*
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* Copyright (C) 2013, 2014 Red Hat, Inc.
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* Author: Mark Salter <msalter@redhat.com>
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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__INIT
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SYM_CODE_START(efi_enter_kernel)
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/*
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* efi_pe_entry() will have copied the kernel image if necessary and we
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* end up here with device tree address in x1 and the kernel entry
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* point stored in x0. Save those values in registers which are
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* callee preserved.
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*/
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ldr w2, =primary_entry_offset
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add x19, x0, x2 // relocated Image entrypoint
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mov x20, x1 // DTB address
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/*
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* Clean the copied Image to the PoC, and ensure it is not shadowed by
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* stale icache entries from before relocation.
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*/
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ldr w1, =kernel_size
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add x1, x0, x1
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bl dcache_clean_poc
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ic ialluis
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/*
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* Clean the remainder of this routine to the PoC
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* so that we can safely disable the MMU and caches.
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*/
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adr x0, 0f
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adr x1, 3f
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bl dcache_clean_poc
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0:
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/* Turn off Dcache and MMU */
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mrs x0, CurrentEL
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cmp x0, #CurrentEL_EL2
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b.ne 1f
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mrs x0, sctlr_el2
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bic x0, x0, #1 << 0 // clear SCTLR.M
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bic x0, x0, #1 << 2 // clear SCTLR.C
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pre_disable_mmu_workaround
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msr sctlr_el2, x0
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isb
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b 2f
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1:
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mrs x0, sctlr_el1
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bic x0, x0, #1 << 0 // clear SCTLR.M
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bic x0, x0, #1 << 2 // clear SCTLR.C
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pre_disable_mmu_workaround
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msr sctlr_el1, x0
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isb
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2:
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/* Jump to kernel entry point */
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mov x0, x20
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mov x1, xzr
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mov x2, xzr
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mov x3, xzr
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br x19
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3:
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SYM_CODE_END(efi_enter_kernel)
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