Tianyu Lan faff44069f x86/hyperv: Add Write/Read MSR registers via ghcb page ... Hyperv provides GHCB protocol to write Synthetic Interrupt Controller MSR registers in Isolation VM with AMD SEV SNP and these registers are emulated by hypervisor directly. Hyperv requires to write SINTx MSR registers twice. First writes MSR via GHCB page to communicate with hypervisor and then writes wrmsr instruction to talk with paravisor which runs in VMPL0. Guest OS ID MSR also needs to be set via GHCB page. Reviewed-by: Michael Kelley <mikelley@microsoft.com> Signed-off-by: Tianyu Lan <Tianyu.Lan@microsoft.com> Link: https://lore.kernel.org/r/20211025122116.264793-7-ltykernel@gmail.com Signed-off-by: Wei Liu <wei.liu@kernel.org>		2021-10-28 11:22:38 +00:00
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hv_apic.c	x86/hyperv: Avoid erroneously sending IPI to 'self'	2021-10-06 15:56:45 +00:00
hv_init.c	x86/hyperv: Add Write/Read MSR registers via ghcb page	2021-10-28 11:22:38 +00:00
hv_proc.c	drivers: hv: Create a consistent pattern for checking Hyper-V hypercall status	2021-04-21 09:49:19 +00:00
hv_spinlock.c	x86/hyperv: Fix unused variable 'msr_val' warning in hv_qlock_wait	2021-03-24 11:31:04 +00:00
irqdomain.c	drivers: hv: Create a consistent pattern for checking Hyper-V hypercall status	2021-04-21 09:49:19 +00:00
ivm.c	x86/hyperv: Add Write/Read MSR registers via ghcb page	2021-10-28 11:22:38 +00:00
Makefile	x86/hyperv: Add new hvcall guest address host visibility support	2021-10-28 11:21:33 +00:00
mmu.c	The x86 MM changes in this cycle were:	2021-04-29 11:41:43 -07:00
nested.c	drivers: hv: Create a consistent pattern for checking Hyper-V hypercall status	2021-04-21 09:49:19 +00:00