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fb1c8f93d8
This patch (written by me and also containing many suggestions of Arjan van de Ven) does a major cleanup of the spinlock code. It does the following things: - consolidates and enhances the spinlock/rwlock debugging code - simplifies the asm/spinlock.h files - encapsulates the raw spinlock type and moves generic spinlock features (such as ->break_lock) into the generic code. - cleans up the spinlock code hierarchy to get rid of the spaghetti. Most notably there's now only a single variant of the debugging code, located in lib/spinlock_debug.c. (previously we had one SMP debugging variant per architecture, plus a separate generic one for UP builds) Also, i've enhanced the rwlock debugging facility, it will now track write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too. All locks have lockup detection now, which will work for both soft and hard spin/rwlock lockups. The arch-level include files now only contain the minimally necessary subset of the spinlock code - all the rest that can be generalized now lives in the generic headers: include/asm-i386/spinlock_types.h | 16 include/asm-x86_64/spinlock_types.h | 16 I have also split up the various spinlock variants into separate files, making it easier to see which does what. The new layout is: SMP | UP ----------------------------|----------------------------------- asm/spinlock_types_smp.h | linux/spinlock_types_up.h linux/spinlock_types.h | linux/spinlock_types.h asm/spinlock_smp.h | linux/spinlock_up.h linux/spinlock_api_smp.h | linux/spinlock_api_up.h linux/spinlock.h | linux/spinlock.h /* * here's the role of the various spinlock/rwlock related include files: * * on SMP builds: * * asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the * initializers * * linux/spinlock_types.h: * defines the generic type and initializers * * asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel * implementations, mostly inline assembly code * * (also included on UP-debug builds:) * * linux/spinlock_api_smp.h: * contains the prototypes for the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. * * on UP builds: * * linux/spinlock_type_up.h: * contains the generic, simplified UP spinlock type. * (which is an empty structure on non-debug builds) * * linux/spinlock_types.h: * defines the generic type and initializers * * linux/spinlock_up.h: * contains the __raw_spin_*()/etc. version of UP * builds. (which are NOPs on non-debug, non-preempt * builds) * * (included on UP-non-debug builds:) * * linux/spinlock_api_up.h: * builds the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. */ All SMP and UP architectures are converted by this patch. arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should be mostly fine. From: Grant Grundler <grundler@parisc-linux.org> Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU). Builds 32-bit SMP kernel (not booted or tested). I did not try to build non-SMP kernels. That should be trivial to fix up later if necessary. I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids some ugly nesting of linux/*.h and asm/*.h files. Those particular locks are well tested and contained entirely inside arch specific code. I do NOT expect any new issues to arise with them. If someone does ever need to use debug/metrics with them, then they will need to unravel this hairball between spinlocks, atomic ops, and bit ops that exist only because parisc has exactly one atomic instruction: LDCW (load and clear word). From: "Luck, Tony" <tony.luck@intel.com> ia64 fix Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjanv@infradead.org> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se> Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
199 lines
5.7 KiB
C
199 lines
5.7 KiB
C
#ifndef _ASM_PARISC_ATOMIC_H_
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#define _ASM_PARISC_ATOMIC_H_
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#include <linux/config.h>
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#include <asm/system.h>
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/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>. */
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* And probably incredibly slow on parisc. OTOH, we don't
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* have to write any serious assembly. prumpf
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*/
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#ifdef CONFIG_SMP
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#include <asm/spinlock.h>
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#include <asm/cache.h> /* we use L1_CACHE_BYTES */
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/* Use an array of spinlocks for our atomic_ts.
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* Hash function to index into a different SPINLOCK.
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* Since "a" is usually an address, use one spinlock per cacheline.
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*/
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# define ATOMIC_HASH_SIZE 4
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# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
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extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
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/* Can't use raw_spin_lock_irq because of #include problems, so
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* this is the substitute */
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#define _atomic_spin_lock_irqsave(l,f) do { \
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raw_spinlock_t *s = ATOMIC_HASH(l); \
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local_irq_save(f); \
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__raw_spin_lock(s); \
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} while(0)
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#define _atomic_spin_unlock_irqrestore(l,f) do { \
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raw_spinlock_t *s = ATOMIC_HASH(l); \
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__raw_spin_unlock(s); \
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local_irq_restore(f); \
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} while(0)
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#else
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# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
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# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
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#endif
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/* Note that we need not lock read accesses - aligned word writes/reads
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* are atomic, so a reader never sees unconsistent values.
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*
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* Cache-line alignment would conflict with, for example, linux/module.h
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*/
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typedef struct { volatile int counter; } atomic_t;
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/* This should get optimized out since it's never called.
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** Or get a link error if xchg is used "wrong".
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*/
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extern void __xchg_called_with_bad_pointer(void);
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/* __xchg32/64 defined in arch/parisc/lib/bitops.c */
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extern unsigned long __xchg8(char, char *);
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extern unsigned long __xchg32(int, int *);
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#ifdef __LP64__
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extern unsigned long __xchg64(unsigned long, unsigned long *);
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#endif
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/* optimizer better get rid of switch since size is a constant */
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static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
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int size)
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{
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switch(size) {
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#ifdef __LP64__
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case 8: return __xchg64(x,(unsigned long *) ptr);
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#endif
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case 4: return __xchg32((int) x, (int *) ptr);
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case 1: return __xchg8((char) x, (char *) ptr);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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/*
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** REVISIT - Abandoned use of LDCW in xchg() for now:
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** o need to test sizeof(*ptr) to avoid clearing adjacent bytes
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** o and while we are at it, could __LP64__ code use LDCD too?
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**
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** if (__builtin_constant_p(x) && (x == NULL))
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** if (((unsigned long)p & 0xf) == 0)
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** return __ldcw(p);
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*/
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define __HAVE_ARCH_CMPXCHG 1
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/* bug catcher for when unsupported size is used - won't link */
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extern void __cmpxchg_called_with_bad_pointer(void);
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/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */
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extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old, unsigned int new_);
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extern unsigned long __cmpxchg_u64(volatile unsigned long *ptr, unsigned long old, unsigned long new_);
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/* don't worry...optimizer will get rid of most of this */
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size)
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{
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switch(size) {
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#ifdef __LP64__
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case 8: return __cmpxchg_u64((unsigned long *)ptr, old, new_);
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#endif
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case 4: return __cmpxchg_u32((unsigned int *)ptr, (unsigned int) old, (unsigned int) new_);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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/* It's possible to reduce all atomic operations to either
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* __atomic_add_return, atomic_set and atomic_read (the latter
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* is there only for consistency).
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*/
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static __inline__ int __atomic_add_return(int i, atomic_t *v)
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{
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int ret;
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unsigned long flags;
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_atomic_spin_lock_irqsave(v, flags);
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ret = (v->counter += i);
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_atomic_spin_unlock_irqrestore(v, flags);
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return ret;
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}
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static __inline__ void atomic_set(atomic_t *v, int i)
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{
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unsigned long flags;
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_atomic_spin_lock_irqsave(v, flags);
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v->counter = i;
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_atomic_spin_unlock_irqrestore(v, flags);
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}
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static __inline__ int atomic_read(const atomic_t *v)
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{
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return v->counter;
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}
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/* exported interface */
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#define atomic_add(i,v) ((void)(__atomic_add_return( ((int)i),(v))))
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#define atomic_sub(i,v) ((void)(__atomic_add_return(-((int)i),(v))))
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#define atomic_inc(v) ((void)(__atomic_add_return( 1,(v))))
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#define atomic_dec(v) ((void)(__atomic_add_return( -1,(v))))
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#define atomic_add_return(i,v) (__atomic_add_return( ((int)i),(v)))
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#define atomic_sub_return(i,v) (__atomic_add_return(-((int)i),(v)))
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#define atomic_inc_return(v) (__atomic_add_return( 1,(v)))
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#define atomic_dec_return(v) (__atomic_add_return( -1,(v)))
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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#define ATOMIC_INIT(i) { (i) }
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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#endif
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