Eugeniy Paltsev fbd1cec570 ARC: [plat-axs103]: Set initial core pll output frequency ... Set initial core pll output frequency specified in device tree to 100MHz for SMP configuration and 90MHz for UP configuration. It will be applied at the core pll driver probing. Update platform quirk for decreasing core frequency for quad core configuration. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2017-12-20 12:41:45 -08:00
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axs10x.c	ARC: [plat-axs103]: Set initial core pll output frequency	2017-12-20 12:41:45 -08:00
Kconfig	ARC: [plat-axs10x] auto-select AXS101 or AXS103 given the ISA config	2017-10-29 16:19:30 -07:00
Makefile	ARC: [axs101] Add support for AXS101 SDP (software development platform)	2015-06-19 18:09:30 +05:30