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![Suman Anna](/assets/img/avatar_default.png)
The omap_dm_timer_set_source() function provides a means for client users to configure the mux parent for a GPTimer's functional clock. However, not all timers are configurable (Eg: Timer12 on DRA7 is fed by an internal 32k oscillator clock, and does not have configurable parent clocks). So, check for such cases and proceed with out throwing an error. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
1005 lines
25 KiB
C
1005 lines
25 KiB
C
/*
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* linux/arch/arm/plat-omap/dmtimer.c
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*
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* OMAP Dual-Mode Timers
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Tarun Kanti DebBarma <tarun.kanti@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* dmtimer adaptation to platform_driver.
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*
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* Copyright (C) 2005 Nokia Corporation
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* OMAP2 support by Juha Yrjola
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* API improvements and OMAP2 clock framework support by Timo Teras
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/dmtimer-omap.h>
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#include <plat/dmtimer.h>
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static u32 omap_reserved_systimers;
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static LIST_HEAD(omap_timer_list);
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static DEFINE_SPINLOCK(dm_timer_lock);
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enum {
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REQUEST_ANY = 0,
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REQUEST_BY_ID,
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REQUEST_BY_CAP,
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REQUEST_BY_NODE,
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};
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/**
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* omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
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* @timer: timer pointer over which read operation to perform
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* @reg: lowest byte holds the register offset
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*
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* The posted mode bit is encoded in reg. Note that in posted mode write
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* pending bit must be checked. Otherwise a read of a non completed write
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* will produce an error.
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*/
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static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
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{
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WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
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return __omap_dm_timer_read(timer, reg, timer->posted);
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}
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/**
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* omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
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* @timer: timer pointer over which write operation is to perform
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* @reg: lowest byte holds the register offset
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* @value: data to write into the register
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*
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* The posted mode bit is encoded in reg. Note that in posted mode the write
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* pending bit must be checked. Otherwise a write on a register which has a
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* pending write will be lost.
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*/
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static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
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u32 value)
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{
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WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
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__omap_dm_timer_write(timer, reg, value, timer->posted);
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}
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static void omap_timer_restore_context(struct omap_dm_timer *timer)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
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timer->context.twer);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
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timer->context.tcrr);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
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timer->context.tldr);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
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timer->context.tmar);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
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timer->context.tsicr);
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writel_relaxed(timer->context.tier, timer->irq_ena);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
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timer->context.tclr);
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}
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static int omap_dm_timer_reset(struct omap_dm_timer *timer)
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{
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u32 l, timeout = 100000;
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if (timer->revision != 1)
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return -EINVAL;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
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do {
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l = __omap_dm_timer_read(timer,
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OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
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} while (!l && timeout--);
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if (!timeout) {
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dev_err(&timer->pdev->dev, "Timer failed to reset\n");
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return -ETIMEDOUT;
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}
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/* Configure timer for smart-idle mode */
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l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
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l |= 0x2 << 0x3;
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__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
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timer->posted = 0;
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return 0;
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}
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static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer)
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{
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int ret;
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struct clk *parent;
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/*
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* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
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* do not call clk_get() for these devices.
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*/
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if (!timer->fclk)
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return -ENODEV;
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parent = clk_get(&timer->pdev->dev, NULL);
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if (IS_ERR(parent))
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return -ENODEV;
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ret = clk_set_parent(timer->fclk, parent);
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if (ret < 0)
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pr_err("%s: failed to set parent\n", __func__);
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clk_put(parent);
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return ret;
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}
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static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
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{
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int rc;
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/*
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* FIXME: OMAP1 devices do not use the clock framework for dmtimers so
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* do not call clk_get() for these devices.
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*/
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if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
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timer->fclk = clk_get(&timer->pdev->dev, "fck");
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if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
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dev_err(&timer->pdev->dev, ": No fclk handle.\n");
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return -EINVAL;
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}
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}
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omap_dm_timer_enable(timer);
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if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
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rc = omap_dm_timer_reset(timer);
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if (rc) {
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omap_dm_timer_disable(timer);
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return rc;
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}
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}
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__omap_dm_timer_enable_posted(timer);
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omap_dm_timer_disable(timer);
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rc = omap_dm_timer_of_set_source(timer);
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if (rc == -ENODEV)
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return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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return rc;
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}
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static inline u32 omap_dm_timer_reserved_systimer(int id)
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{
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return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
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}
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int omap_dm_timer_reserve_systimer(int id)
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{
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if (omap_dm_timer_reserved_systimer(id))
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return -ENODEV;
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omap_reserved_systimers |= (1 << (id - 1));
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return 0;
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}
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static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
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{
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struct omap_dm_timer *timer = NULL, *t;
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struct device_node *np = NULL;
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unsigned long flags;
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u32 cap = 0;
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int id = 0;
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switch (req_type) {
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case REQUEST_BY_ID:
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id = *(int *)data;
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break;
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case REQUEST_BY_CAP:
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cap = *(u32 *)data;
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break;
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case REQUEST_BY_NODE:
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np = (struct device_node *)data;
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break;
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default:
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/* REQUEST_ANY */
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break;
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}
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spin_lock_irqsave(&dm_timer_lock, flags);
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list_for_each_entry(t, &omap_timer_list, node) {
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if (t->reserved)
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continue;
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switch (req_type) {
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case REQUEST_BY_ID:
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if (id == t->pdev->id) {
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timer = t;
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timer->reserved = 1;
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goto found;
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}
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break;
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case REQUEST_BY_CAP:
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if (cap == (t->capability & cap)) {
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/*
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* If timer is not NULL, we have already found
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* one timer but it was not an exact match
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* because it had more capabilites that what
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* was required. Therefore, unreserve the last
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* timer found and see if this one is a better
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* match.
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*/
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if (timer)
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timer->reserved = 0;
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timer = t;
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timer->reserved = 1;
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/* Exit loop early if we find an exact match */
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if (t->capability == cap)
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goto found;
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}
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break;
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case REQUEST_BY_NODE:
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if (np == t->pdev->dev.of_node) {
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timer = t;
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timer->reserved = 1;
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goto found;
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}
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break;
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default:
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/* REQUEST_ANY */
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timer = t;
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timer->reserved = 1;
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goto found;
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}
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}
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found:
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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if (timer && omap_dm_timer_prepare(timer)) {
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timer->reserved = 0;
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timer = NULL;
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}
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if (!timer)
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pr_debug("%s: timer request failed!\n", __func__);
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return timer;
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}
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struct omap_dm_timer *omap_dm_timer_request(void)
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{
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return _omap_dm_timer_request(REQUEST_ANY, NULL);
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_request);
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struct omap_dm_timer *omap_dm_timer_request_specific(int id)
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{
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/* Requesting timer by ID is not supported when device tree is used */
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if (of_have_populated_dt()) {
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pr_warn("%s: Please use omap_dm_timer_request_by_cap/node()\n",
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__func__);
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return NULL;
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}
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return _omap_dm_timer_request(REQUEST_BY_ID, &id);
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
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/**
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* omap_dm_timer_request_by_cap - Request a timer by capability
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* @cap: Bit mask of capabilities to match
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*
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* Find a timer based upon capabilities bit mask. Callers of this function
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* should use the definitions found in the plat/dmtimer.h file under the
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* comment "timer capabilities used in hwmod database". Returns pointer to
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* timer handle on success and a NULL pointer on failure.
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*/
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struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
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{
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return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
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/**
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* omap_dm_timer_request_by_node - Request a timer by device-tree node
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* @np: Pointer to device-tree timer node
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*
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* Request a timer based upon a device node pointer. Returns pointer to
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* timer handle on success and a NULL pointer on failure.
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*/
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struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
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{
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if (!np)
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return NULL;
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return _omap_dm_timer_request(REQUEST_BY_NODE, np);
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_node);
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int omap_dm_timer_free(struct omap_dm_timer *timer)
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{
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if (unlikely(!timer))
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return -EINVAL;
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clk_put(timer->fclk);
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WARN_ON(!timer->reserved);
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timer->reserved = 0;
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return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_free);
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void omap_dm_timer_enable(struct omap_dm_timer *timer)
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{
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int c;
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pm_runtime_get_sync(&timer->pdev->dev);
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if (!(timer->capability & OMAP_TIMER_ALWON)) {
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if (timer->get_context_loss_count) {
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c = timer->get_context_loss_count(&timer->pdev->dev);
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if (c != timer->ctx_loss_count) {
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omap_timer_restore_context(timer);
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timer->ctx_loss_count = c;
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}
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} else {
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omap_timer_restore_context(timer);
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}
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}
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
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void omap_dm_timer_disable(struct omap_dm_timer *timer)
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{
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pm_runtime_put_sync(&timer->pdev->dev);
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
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{
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if (timer)
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return timer->irq;
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
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#if defined(CONFIG_ARCH_OMAP1)
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#include <mach/hardware.h>
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/**
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* omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
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* @inputmask: current value of idlect mask
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*/
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
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{
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int i = 0;
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struct omap_dm_timer *timer = NULL;
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unsigned long flags;
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/* If ARMXOR cannot be idled this function call is unnecessary */
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if (!(inputmask & (1 << 1)))
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return inputmask;
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/* If any active timer is using ARMXOR return modified mask */
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spin_lock_irqsave(&dm_timer_lock, flags);
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list_for_each_entry(timer, &omap_timer_list, node) {
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u32 l;
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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if (l & OMAP_TIMER_CTRL_ST) {
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if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
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inputmask &= ~(1 << 1);
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else
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inputmask &= ~(1 << 2);
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}
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i++;
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}
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spin_unlock_irqrestore(&dm_timer_lock, flags);
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return inputmask;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
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#else
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struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
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{
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if (timer && !IS_ERR(timer->fclk))
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return timer->fclk;
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return NULL;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
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{
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BUG();
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return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
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#endif
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int omap_dm_timer_trigger(struct omap_dm_timer *timer)
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{
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if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
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pr_err("%s: timer not available or enabled.\n", __func__);
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return -EINVAL;
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}
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omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
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return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
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int omap_dm_timer_start(struct omap_dm_timer *timer)
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{
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u32 l;
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if (unlikely(!timer))
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return -EINVAL;
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omap_dm_timer_enable(timer);
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
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if (!(l & OMAP_TIMER_CTRL_ST)) {
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l |= OMAP_TIMER_CTRL_ST;
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
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}
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/* Save the context */
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timer->context.tclr = l;
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return 0;
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}
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EXPORT_SYMBOL_GPL(omap_dm_timer_start);
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int omap_dm_timer_stop(struct omap_dm_timer *timer)
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{
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unsigned long rate = 0;
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if (unlikely(!timer))
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return -EINVAL;
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if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
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rate = clk_get_rate(timer->fclk);
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__omap_dm_timer_stop(timer, timer->posted, rate);
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/*
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* Since the register values are computed and written within
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* __omap_dm_timer_stop, we need to use read to retrieve the
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* context.
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*/
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timer->context.tclr =
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omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
|
omap_dm_timer_disable(timer);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
|
|
|
|
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
|
|
{
|
|
int ret;
|
|
char *parent_name = NULL;
|
|
struct clk *parent;
|
|
struct dmtimer_platform_data *pdata;
|
|
|
|
if (unlikely(!timer))
|
|
return -EINVAL;
|
|
|
|
pdata = timer->pdev->dev.platform_data;
|
|
|
|
if (source < 0 || source >= 3)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* FIXME: Used for OMAP1 devices only because they do not currently
|
|
* use the clock framework to set the parent clock. To be removed
|
|
* once OMAP1 migrated to using clock framework for dmtimers
|
|
*/
|
|
if (pdata && pdata->set_timer_src)
|
|
return pdata->set_timer_src(timer->pdev, source);
|
|
|
|
if (IS_ERR(timer->fclk))
|
|
return -EINVAL;
|
|
|
|
#if defined(CONFIG_COMMON_CLK)
|
|
/* Check if the clock has configurable parents */
|
|
if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
|
|
return 0;
|
|
#endif
|
|
|
|
switch (source) {
|
|
case OMAP_TIMER_SRC_SYS_CLK:
|
|
parent_name = "timer_sys_ck";
|
|
break;
|
|
|
|
case OMAP_TIMER_SRC_32_KHZ:
|
|
parent_name = "timer_32k_ck";
|
|
break;
|
|
|
|
case OMAP_TIMER_SRC_EXT_CLK:
|
|
parent_name = "timer_ext_ck";
|
|
break;
|
|
}
|
|
|
|
parent = clk_get(&timer->pdev->dev, parent_name);
|
|
if (IS_ERR(parent)) {
|
|
pr_err("%s: %s not found\n", __func__, parent_name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = clk_set_parent(timer->fclk, parent);
|
|
if (ret < 0)
|
|
pr_err("%s: failed to set %s as parent\n", __func__,
|
|
parent_name);
|
|
|
|
clk_put(parent);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
|
|
|
|
int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
|
|
unsigned int load)
|
|
{
|
|
u32 l;
|
|
|
|
if (unlikely(!timer))
|
|
return -EINVAL;
|
|
|
|
omap_dm_timer_enable(timer);
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
|
if (autoreload)
|
|
l |= OMAP_TIMER_CTRL_AR;
|
|
else
|
|
l &= ~OMAP_TIMER_CTRL_AR;
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
|
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
|
|
/* Save the context */
|
|
timer->context.tclr = l;
|
|
timer->context.tldr = load;
|
|
omap_dm_timer_disable(timer);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
|
|
|
|
/* Optimized set_load which removes costly spin wait in timer_start */
|
|
int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
|
|
unsigned int load)
|
|
{
|
|
u32 l;
|
|
|
|
if (unlikely(!timer))
|
|
return -EINVAL;
|
|
|
|
omap_dm_timer_enable(timer);
|
|
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
|
if (autoreload) {
|
|
l |= OMAP_TIMER_CTRL_AR;
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
|
|
} else {
|
|
l &= ~OMAP_TIMER_CTRL_AR;
|
|
}
|
|
l |= OMAP_TIMER_CTRL_ST;
|
|
|
|
__omap_dm_timer_load_start(timer, l, load, timer->posted);
|
|
|
|
/* Save the context */
|
|
timer->context.tclr = l;
|
|
timer->context.tldr = load;
|
|
timer->context.tcrr = load;
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
|
|
|
|
int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
|
|
unsigned int match)
|
|
{
|
|
u32 l;
|
|
|
|
if (unlikely(!timer))
|
|
return -EINVAL;
|
|
|
|
omap_dm_timer_enable(timer);
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
|
if (enable)
|
|
l |= OMAP_TIMER_CTRL_CE;
|
|
else
|
|
l &= ~OMAP_TIMER_CTRL_CE;
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
|
|
|
/* Save the context */
|
|
timer->context.tclr = l;
|
|
timer->context.tmar = match;
|
|
omap_dm_timer_disable(timer);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
|
|
|
|
int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
|
|
int toggle, int trigger)
|
|
{
|
|
u32 l;
|
|
|
|
if (unlikely(!timer))
|
|
return -EINVAL;
|
|
|
|
omap_dm_timer_enable(timer);
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
|
l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
|
|
OMAP_TIMER_CTRL_PT | (0x03 << 10));
|
|
if (def_on)
|
|
l |= OMAP_TIMER_CTRL_SCPWM;
|
|
if (toggle)
|
|
l |= OMAP_TIMER_CTRL_PT;
|
|
l |= trigger << 10;
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
|
|
|
/* Save the context */
|
|
timer->context.tclr = l;
|
|
omap_dm_timer_disable(timer);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
|
|
|
|
int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
|
|
{
|
|
u32 l;
|
|
|
|
if (unlikely(!timer))
|
|
return -EINVAL;
|
|
|
|
omap_dm_timer_enable(timer);
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
|
l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
|
|
if (prescaler >= 0x00 && prescaler <= 0x07) {
|
|
l |= OMAP_TIMER_CTRL_PRE;
|
|
l |= prescaler << 2;
|
|
}
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
|
|
|
|
/* Save the context */
|
|
timer->context.tclr = l;
|
|
omap_dm_timer_disable(timer);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
|
|
|
|
int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
|
|
unsigned int value)
|
|
{
|
|
if (unlikely(!timer))
|
|
return -EINVAL;
|
|
|
|
omap_dm_timer_enable(timer);
|
|
__omap_dm_timer_int_enable(timer, value);
|
|
|
|
/* Save the context */
|
|
timer->context.tier = value;
|
|
timer->context.twer = value;
|
|
omap_dm_timer_disable(timer);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
|
|
|
|
/**
|
|
* omap_dm_timer_set_int_disable - disable timer interrupts
|
|
* @timer: pointer to timer handle
|
|
* @mask: bit mask of interrupts to be disabled
|
|
*
|
|
* Disables the specified timer interrupts for a timer.
|
|
*/
|
|
int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
|
|
{
|
|
u32 l = mask;
|
|
|
|
if (unlikely(!timer))
|
|
return -EINVAL;
|
|
|
|
omap_dm_timer_enable(timer);
|
|
|
|
if (timer->revision == 1)
|
|
l = readl_relaxed(timer->irq_ena) & ~mask;
|
|
|
|
writel_relaxed(l, timer->irq_dis);
|
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
|
|
|
|
/* Save the context */
|
|
timer->context.tier &= ~mask;
|
|
timer->context.twer &= ~mask;
|
|
omap_dm_timer_disable(timer);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
|
|
|
|
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
|
|
{
|
|
unsigned int l;
|
|
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
|
|
pr_err("%s: timer not available or enabled.\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
l = readl_relaxed(timer->irq_stat);
|
|
|
|
return l;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
|
|
|
|
int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
|
|
{
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
|
|
return -EINVAL;
|
|
|
|
__omap_dm_timer_write_status(timer, value);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
|
|
|
|
unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
|
|
{
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
|
|
pr_err("%s: timer not iavailable or enabled.\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
return __omap_dm_timer_read_counter(timer, timer->posted);
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
|
|
|
|
int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
|
|
{
|
|
if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
|
|
pr_err("%s: timer not available or enabled.\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
|
|
|
|
/* Save the context */
|
|
timer->context.tcrr = value;
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
|
|
|
|
int omap_dm_timers_active(void)
|
|
{
|
|
struct omap_dm_timer *timer;
|
|
|
|
list_for_each_entry(timer, &omap_timer_list, node) {
|
|
if (!timer->reserved)
|
|
continue;
|
|
|
|
if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
|
|
OMAP_TIMER_CTRL_ST) {
|
|
return 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(omap_dm_timers_active);
|
|
|
|
static const struct of_device_id omap_timer_match[];
|
|
|
|
/**
|
|
* omap_dm_timer_probe - probe function called for every registered device
|
|
* @pdev: pointer to current timer platform device
|
|
*
|
|
* Called by driver framework at the end of device registration for all
|
|
* timer devices.
|
|
*/
|
|
static int omap_dm_timer_probe(struct platform_device *pdev)
|
|
{
|
|
unsigned long flags;
|
|
struct omap_dm_timer *timer;
|
|
struct resource *mem, *irq;
|
|
struct device *dev = &pdev->dev;
|
|
const struct of_device_id *match;
|
|
const struct dmtimer_platform_data *pdata;
|
|
int ret;
|
|
|
|
match = of_match_device(of_match_ptr(omap_timer_match), dev);
|
|
pdata = match ? match->data : dev->platform_data;
|
|
|
|
if (!pdata && !dev->of_node) {
|
|
dev_err(dev, "%s: no platform data.\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
if (unlikely(!irq)) {
|
|
dev_err(dev, "%s: no IRQ resource.\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (unlikely(!mem)) {
|
|
dev_err(dev, "%s: no memory resource.\n", __func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL);
|
|
if (!timer) {
|
|
dev_err(dev, "%s: memory alloc failed!\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
timer->fclk = ERR_PTR(-ENODEV);
|
|
timer->io_base = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(timer->io_base))
|
|
return PTR_ERR(timer->io_base);
|
|
|
|
if (dev->of_node) {
|
|
if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
|
|
timer->capability |= OMAP_TIMER_ALWON;
|
|
if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
|
|
timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
|
|
if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
|
|
timer->capability |= OMAP_TIMER_HAS_PWM;
|
|
if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
|
|
timer->capability |= OMAP_TIMER_SECURE;
|
|
} else {
|
|
timer->id = pdev->id;
|
|
timer->capability = pdata->timer_capability;
|
|
timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
|
|
timer->get_context_loss_count = pdata->get_context_loss_count;
|
|
}
|
|
|
|
if (pdata)
|
|
timer->errata = pdata->timer_errata;
|
|
|
|
timer->irq = irq->start;
|
|
timer->pdev = pdev;
|
|
|
|
/* Skip pm_runtime_enable for OMAP1 */
|
|
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_irq_safe(dev);
|
|
}
|
|
|
|
if (!timer->reserved) {
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
|
|
__func__);
|
|
goto err_get_sync;
|
|
}
|
|
__omap_dm_timer_init_regs(timer);
|
|
pm_runtime_put(dev);
|
|
}
|
|
|
|
/* add the timer element to the list */
|
|
spin_lock_irqsave(&dm_timer_lock, flags);
|
|
list_add_tail(&timer->node, &omap_timer_list);
|
|
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
|
|
|
dev_dbg(dev, "Device Probed.\n");
|
|
|
|
return 0;
|
|
|
|
err_get_sync:
|
|
pm_runtime_put_noidle(dev);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* omap_dm_timer_remove - cleanup a registered timer device
|
|
* @pdev: pointer to current timer platform device
|
|
*
|
|
* Called by driver framework whenever a timer device is unregistered.
|
|
* In addition to freeing platform resources it also deletes the timer
|
|
* entry from the local list.
|
|
*/
|
|
static int omap_dm_timer_remove(struct platform_device *pdev)
|
|
{
|
|
struct omap_dm_timer *timer;
|
|
unsigned long flags;
|
|
int ret = -EINVAL;
|
|
|
|
spin_lock_irqsave(&dm_timer_lock, flags);
|
|
list_for_each_entry(timer, &omap_timer_list, node)
|
|
if (!strcmp(dev_name(&timer->pdev->dev),
|
|
dev_name(&pdev->dev))) {
|
|
list_del(&timer->node);
|
|
ret = 0;
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dmtimer_platform_data omap3plus_pdata = {
|
|
.timer_errata = OMAP_TIMER_ERRATA_I103_I767,
|
|
};
|
|
|
|
static const struct of_device_id omap_timer_match[] = {
|
|
{
|
|
.compatible = "ti,omap2420-timer",
|
|
},
|
|
{
|
|
.compatible = "ti,omap3430-timer",
|
|
.data = &omap3plus_pdata,
|
|
},
|
|
{
|
|
.compatible = "ti,omap4430-timer",
|
|
.data = &omap3plus_pdata,
|
|
},
|
|
{
|
|
.compatible = "ti,omap5430-timer",
|
|
.data = &omap3plus_pdata,
|
|
},
|
|
{
|
|
.compatible = "ti,am335x-timer",
|
|
.data = &omap3plus_pdata,
|
|
},
|
|
{
|
|
.compatible = "ti,am335x-timer-1ms",
|
|
.data = &omap3plus_pdata,
|
|
},
|
|
{
|
|
.compatible = "ti,dm816-timer",
|
|
.data = &omap3plus_pdata,
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, omap_timer_match);
|
|
|
|
static struct platform_driver omap_dm_timer_driver = {
|
|
.probe = omap_dm_timer_probe,
|
|
.remove = omap_dm_timer_remove,
|
|
.driver = {
|
|
.name = "omap_timer",
|
|
.of_match_table = of_match_ptr(omap_timer_match),
|
|
},
|
|
};
|
|
|
|
early_platform_init("earlytimer", &omap_dm_timer_driver);
|
|
module_platform_driver(omap_dm_timer_driver);
|
|
|
|
MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
MODULE_AUTHOR("Texas Instruments Inc");
|