Paolo Bonzini fc46f8a115 KVM: x86: use CPUID to locate host page table reserved bits ... [ Upstream commit 7adacf5eb2 ] The comment in kvm_get_shadow_phys_bits refers to MKTME, but the same is actually true of SME and SEV. Just use CPUID[0x8000_0008].EAX[7:0] unconditionally if available, it is simplest and works even if memory is not encrypted. Cc: stable@vger.kernel.org Reported-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2020-02-11 04:35:53 -08:00
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alpha
arc
arm	ARM: tegra: Enable PLLP bypass during Tegra124 LP1	2020-02-11 04:35:34 -08:00
arm64	arm64: dts: qcom: qcs404-evb: Set vdd_apc regulator in high power mode	2020-02-11 04:35:42 -08:00
c6x
csky
h8300
hexagon
ia64
m68k
microblaze
mips	MIPS: boot: fix typo in 'vmlinux.lzma.its' target	2020-02-11 04:35:17 -08:00
nds32
nios2
openrisc
parisc	parisc: Use proper printk format for resource_size_t	2020-02-05 21:22:46 +00:00
powerpc	powerpc/44x: Adjust indentation in ibm4xx_denali_fixup_memsize	2020-02-11 04:35:45 -08:00
riscv	riscv, bpf: Fix broken BPF tail calls	2020-02-11 04:35:28 -08:00
s390	KVM: s390: do not clobber registers during guest reset/store status	2020-02-11 04:35:42 -08:00
sh
sparc	mm/mmu_gather: invalidate TLB correctly on batch allocation failure and flush	2020-02-11 04:35:42 -08:00
um
unicore32
x86	KVM: x86: use CPUID to locate host page table reserved bits	2020-02-11 04:35:53 -08:00
xtensa
.gitignore
Kconfig	mm/mmu_gather: invalidate TLB correctly on batch allocation failure and flush	2020-02-11 04:35:42 -08:00