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e873d4329c
The hdmi script already supported in sdma firmware. So add support hdmi in sdma driver. The design of hdmi script is different from common script such as sai. There is no need to config buffer descriptor for HDMI. The cyclic capability is achieved by the hdmi script. The slave config is so simple, only config src_addr, dts_addr and direction DMA_TRANS_NONE. Signed-off-by: Joy Zou <joy.zou@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20221115093823.2879128-3-joy.zou@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
102 lines
3.4 KiB
C
102 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef __LINUX_DMA_IMX_H
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#define __LINUX_DMA_IMX_H
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#include <linux/scatterlist.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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/*
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* This enumerates peripheral types. Used for SDMA.
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*/
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enum sdma_peripheral_type {
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IMX_DMATYPE_SSI, /* MCU domain SSI */
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IMX_DMATYPE_SSI_SP, /* Shared SSI */
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IMX_DMATYPE_MMC, /* MMC */
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IMX_DMATYPE_SDHC, /* SDHC */
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IMX_DMATYPE_UART, /* MCU domain UART */
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IMX_DMATYPE_UART_SP, /* Shared UART */
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IMX_DMATYPE_FIRI, /* FIRI */
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IMX_DMATYPE_CSPI, /* MCU domain CSPI */
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IMX_DMATYPE_CSPI_SP, /* Shared CSPI */
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IMX_DMATYPE_SIM, /* SIM */
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IMX_DMATYPE_ATA, /* ATA */
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IMX_DMATYPE_CCM, /* CCM */
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IMX_DMATYPE_EXT, /* External peripheral */
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IMX_DMATYPE_MSHC, /* Memory Stick Host Controller */
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IMX_DMATYPE_MSHC_SP, /* Shared Memory Stick Host Controller */
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IMX_DMATYPE_DSP, /* DSP */
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IMX_DMATYPE_MEMORY, /* Memory */
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IMX_DMATYPE_FIFO_MEMORY,/* FIFO type Memory */
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IMX_DMATYPE_SPDIF, /* SPDIF */
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IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
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IMX_DMATYPE_ASRC, /* ASRC */
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IMX_DMATYPE_ESAI, /* ESAI */
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IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
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IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
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IMX_DMATYPE_SAI, /* SAI */
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IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
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IMX_DMATYPE_HDMI, /* HDMI Audio */
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};
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enum imx_dma_prio {
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DMA_PRIO_HIGH = 0,
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DMA_PRIO_MEDIUM = 1,
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DMA_PRIO_LOW = 2
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};
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struct imx_dma_data {
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int dma_request; /* DMA request line */
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int dma_request2; /* secondary DMA request line */
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enum sdma_peripheral_type peripheral_type;
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int priority;
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};
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static inline int imx_dma_is_ipu(struct dma_chan *chan)
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{
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return !strcmp(dev_name(chan->device->dev), "ipu-core");
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}
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static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
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{
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return !strcmp(chan->device->dev->driver->name, "imx-sdma") ||
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!strcmp(chan->device->dev->driver->name, "imx-dma");
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}
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/**
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* struct sdma_peripheral_config - SDMA config for audio
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* @n_fifos_src: Number of FIFOs for recording
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* @n_fifos_dst: Number of FIFOs for playback
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* @stride_fifos_src: FIFO address stride for recording, 0 means all FIFOs are
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* continuous, 1 means 1 word stride between FIFOs. All stride
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* between FIFOs should be same.
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* @stride_fifos_dst: FIFO address stride for playback
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* @words_per_fifo: numbers of words per FIFO fetch/fill, 1 means
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* one channel per FIFO, 2 means 2 channels per FIFO..
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* If 'n_fifos_src = 4' and 'words_per_fifo = 2', it
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* means the first two words(channels) fetch from FIFO0
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* and then jump to FIFO1 for next two words, and so on
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* after the last FIFO3 fetched, roll back to FIFO0.
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* @sw_done: Use software done. Needed for PDM (micfil)
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*
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* Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO
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* registers. For multichannel recording/playback the SAI/micfil have
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* one FIFO register per channel and the SDMA engine has to read/write
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* the next channel from/to the next register and wrap around to the
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* first register when all channels are handled. The number of active
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* channels must be communicated to the SDMA engine using this struct.
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*/
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struct sdma_peripheral_config {
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int n_fifos_src;
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int n_fifos_dst;
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int stride_fifos_src;
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int stride_fifos_dst;
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int words_per_fifo;
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bool sw_done;
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};
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#endif /* __LINUX_DMA_IMX_H */
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