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i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being configured to handle 8kHz and 11kHz series audio rates. Add common function in fsl_utils to handle these two PLL clock source, which are needed by CPU DAI drivers Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1656667961-1799-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
29 lines
764 B
C
29 lines
764 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Freescale ALSA SoC Machine driver utility
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*/
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#ifndef _FSL_UTILS_H
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#define _FSL_UTILS_H
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#define DAI_NAME_SIZE 32
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struct snd_soc_dai_link;
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struct device_node;
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int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
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struct snd_soc_dai_link *dai,
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unsigned int *dma_channel_id,
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unsigned int *dma_id);
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void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk,
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struct clk **pll11k_clk);
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void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
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struct clk *pll8k_clk,
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struct clk *pll11k_clk, u64 ratio);
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#endif /* _FSL_UTILS_H */
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