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The Mixer supports mixing of up to ten 7.1 audio input streams and generate five outputs (each of which can be any combination of the ten input streams) This patch registers Mixer driver with ASoC framework. The component driver exposes DAPM widgets, routes and kcontrols for the device. The DAI driver exposes Mixer interfaces, which can be used to connect different components in the ASoC layer. Makefile and Kconfig support is added to allow build the driver. It can be enabled in the DT via "nvidia,tegra210-amixer" compatible binding. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Link: https://lore.kernel.org/r/1631551342-25469-11-git-send-email-spujar@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
100 lines
4 KiB
C
100 lines
4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_mixer.h - Definitions for Tegra210 MIXER driver
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*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_MIXER_H__
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#define __TEGRA210_MIXER_H__
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/* XBAR_RX related MIXER offsets */
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#define TEGRA210_MIXER_RX1_SOFT_RESET 0x04
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#define TEGRA210_MIXER_RX1_STATUS 0x10
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#define TEGRA210_MIXER_RX1_CIF_CTRL 0x24
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#define TEGRA210_MIXER_RX1_CTRL 0x28
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#define TEGRA210_MIXER_RX1_PEAK_CTRL 0x2c
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#define TEGRA210_MIXER_RX1_SAMPLE_COUNT 0x30
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/* XBAR_TX related MIXER offsets */
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#define TEGRA210_MIXER_TX1_ENABLE 0x280
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#define TEGRA210_MIXER_TX1_SOFT_RESET 0x284
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#define TEGRA210_MIXER_TX1_STATUS 0x290
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#define TEGRA210_MIXER_TX1_INT_STATUS 0x294
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#define TEGRA210_MIXER_TX1_INT_MASK 0x298
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#define TEGRA210_MIXER_TX1_INT_SET 0x29c
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#define TEGRA210_MIXER_TX1_INT_CLEAR 0x2a0
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#define TEGRA210_MIXER_TX1_CIF_CTRL 0x2a4
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#define TEGRA210_MIXER_TX1_ADDER_CONFIG 0x2a8
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/* MIXER related offsets */
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#define TEGRA210_MIXER_ENABLE 0x400
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#define TEGRA210_MIXER_SOFT_RESET 0x404
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#define TEGRA210_MIXER_CG 0x408
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#define TEGRA210_MIXER_STATUS 0x410
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#define TEGRA210_MIXER_INT_STATUS 0x414
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#define TEGRA210_MIXER_GAIN_CFG_RAM_CTRL 0x42c
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#define TEGRA210_MIXER_GAIN_CFG_RAM_DATA 0x430
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#define TEGRA210_MIXER_PEAKM_RAM_CTRL 0x434
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#define TEGRA210_MIXER_PEAKM_RAM_DATA 0x438
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#define TEGRA210_MIXER_CTRL 0x43c
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#define TEGRA210_MIXER_TX2_ADDER_CONFIG (TEGRA210_MIXER_TX1_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
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#define TEGRA210_MIXER_TX3_ADDER_CONFIG (TEGRA210_MIXER_TX2_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
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#define TEGRA210_MIXER_TX4_ADDER_CONFIG (TEGRA210_MIXER_TX3_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
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#define TEGRA210_MIXER_TX5_ADDER_CONFIG (TEGRA210_MIXER_TX4_ADDER_CONFIG + TEGRA210_MIXER_REG_STRIDE)
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#define TEGRA210_MIXER_TX2_ENABLE (TEGRA210_MIXER_TX1_ENABLE + TEGRA210_MIXER_REG_STRIDE)
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#define TEGRA210_MIXER_TX3_ENABLE (TEGRA210_MIXER_TX2_ENABLE + TEGRA210_MIXER_REG_STRIDE)
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#define TEGRA210_MIXER_TX4_ENABLE (TEGRA210_MIXER_TX3_ENABLE + TEGRA210_MIXER_REG_STRIDE)
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#define TEGRA210_MIXER_TX5_ENABLE (TEGRA210_MIXER_TX4_ENABLE + TEGRA210_MIXER_REG_STRIDE)
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/* Fields in TEGRA210_MIXER_ENABLE */
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#define TEGRA210_MIXER_ENABLE_SHIFT 0
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#define TEGRA210_MIXER_ENABLE_MASK (1 << TEGRA210_MIXER_ENABLE_SHIFT)
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#define TEGRA210_MIXER_EN (1 << TEGRA210_MIXER_ENABLE_SHIFT)
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/* Fields in TEGRA210_MIXER_GAIN_CFG_RAM_CTRL */
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#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_0 0x0
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#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_STRIDE 0x10
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#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT 14
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#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_MASK (1 << TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT)
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#define TEGRA210_MIXER_GAIN_CFG_RAM_RW_WRITE (1 << TEGRA210_MIXER_GAIN_CFG_RAM_RW_SHIFT)
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#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT 13
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#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_MASK (1 << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN (1 << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT 12
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#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_MASK (1 << TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN (1 << TEGRA210_MIXER_GAIN_CFG_RAM_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT 0
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#define TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_MASK (0x1ff << TEGRA210_MIXER_GAIN_CFG_RAM_ADDR_SHIFT)
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#define TEGRA210_MIXER_REG_STRIDE 0x40
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#define TEGRA210_MIXER_RX_MAX 10
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#define TEGRA210_MIXER_RX_LIMIT (TEGRA210_MIXER_RX_MAX * TEGRA210_MIXER_REG_STRIDE)
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#define TEGRA210_MIXER_TX_MAX 5
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#define TEGRA210_MIXER_TX_LIMIT (TEGRA210_MIXER_RX_LIMIT + (TEGRA210_MIXER_TX_MAX * TEGRA210_MIXER_REG_STRIDE))
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#define REG_CFG_DONE_TRIGGER 0xf
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#define VAL_CFG_DONE_TRIGGER 0x1
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#define NUM_GAIN_POLY_COEFFS 9
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#define NUM_DURATION_PARMS 4
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struct tegra210_mixer_gain_params {
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int poly_coeff[NUM_GAIN_POLY_COEFFS];
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int gain_value;
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int duration[NUM_DURATION_PARMS];
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};
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struct tegra210_mixer {
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int gain_value[TEGRA210_MIXER_RX_MAX];
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struct regmap *regmap;
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};
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#endif
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