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30ad527a64
On Exynos SoCs it is necessary to resume operation of L2C early in assembly code, because otherwise certain systems will crash. This patch adds necessary code to non-secure resume handler. [rewrote the code accessing l2x0_saved_regs] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
131 lines
2.9 KiB
ArmAsm
131 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Exynos low-level resume code
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "smc.h"
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#define CPU_MASK 0xff0ffff0
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#define CPU_CORTEX_A9 0x410fc090
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/*
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* The following code is located into the .data section. This is to
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* allow l2x0_regs_phys to be accessed with a relative load while we
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* can't rely on any MMU translation. We could have put l2x0_regs_phys
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* in the .text section as well, but some setups might insist on it to
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* be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
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*/
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.data
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.align
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/*
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* sleep magic, to allow the bootloader to check for an valid
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* image to resume to. Must be the first word before the
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* exynos_cpu_resume entry.
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*/
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.word 0x2bedf00d
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/*
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* exynos_cpu_resume
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*
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* resume code entry for bootloader to call
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*/
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ENTRY(exynos_cpu_resume)
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#ifdef CONFIG_CACHE_L2X0
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mrc p15, 0, r0, c0, c0, 0
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ldr r1, =CPU_MASK
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and r0, r0, r1
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ldr r1, =CPU_CORTEX_A9
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cmp r0, r1
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bleq l2c310_early_resume
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#endif
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b cpu_resume
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ENDPROC(exynos_cpu_resume)
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.align
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ENTRY(exynos_cpu_resume_ns)
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mrc p15, 0, r0, c0, c0, 0
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ldr r1, =CPU_MASK
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and r0, r0, r1
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ldr r1, =CPU_CORTEX_A9
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cmp r0, r1
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bne skip_cp15
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adr r0, cp15_save_power
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ldr r1, [r0]
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adr r0, cp15_save_diag
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ldr r2, [r0]
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mov r0, #SMC_CMD_C15RESUME
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dsb
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smc #0
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#ifdef CONFIG_CACHE_L2X0
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adr r0, 1f
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ldr r2, [r0]
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add r0, r2, r0
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/* Check that the address has been initialised. */
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ldr r1, [r0, #L2X0_R_PHY_BASE]
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teq r1, #0
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beq skip_l2x0
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/* Check if controller has been enabled. */
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ldr r2, [r1, #L2X0_CTRL]
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tst r2, #0x1
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bne skip_l2x0
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ldr r1, [r0, #L2X0_R_TAG_LATENCY]
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ldr r2, [r0, #L2X0_R_DATA_LATENCY]
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ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
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mov r0, #SMC_CMD_L2X0SETUP1
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smc #0
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/* Reload saved regs pointer because smc corrupts registers. */
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adr r0, 1f
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ldr r2, [r0]
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add r0, r2, r0
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ldr r1, [r0, #L2X0_R_PWR_CTRL]
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ldr r2, [r0, #L2X0_R_AUX_CTRL]
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mov r0, #SMC_CMD_L2X0SETUP2
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smc #0
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mov r0, #SMC_CMD_L2X0INVALL
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smc #0
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mov r1, #1
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mov r0, #SMC_CMD_L2X0CTRL
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smc #0
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skip_l2x0:
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#endif /* CONFIG_CACHE_L2X0 */
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skip_cp15:
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b cpu_resume
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ENDPROC(exynos_cpu_resume_ns)
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.globl cp15_save_diag
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cp15_save_diag:
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.long 0 @ cp15 diagnostic
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.globl cp15_save_power
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cp15_save_power:
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.long 0 @ cp15 power control
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#ifdef CONFIG_CACHE_L2X0
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.align
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1: .long l2x0_saved_regs - .
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#endif /* CONFIG_CACHE_L2X0 */
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