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![Lad Prabhakar](/assets/img/avatar_default.png)
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211224161334.31123-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
967 lines
26 KiB
C
967 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
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*
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* Copyright (C) 2018 Jacob Feder
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*
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* Authors: Jacob Feder <jacobsfeder@gmail.com>
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*
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* See Xilinx PG080 document for IP details
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*/
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/* ----------------------------
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* includes
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* ----------------------------
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*/
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#include <linux/kernel.h>
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#include <linux/wait.h>
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#include <linux/mutex.h>
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#include <linux/device.h>
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#include <linux/cdev.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/moduleparam.h>
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#include <linux/interrupt.h>
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#include <linux/param.h>
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#include <linux/fs.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include <linux/jiffies.h>
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#include <linux/miscdevice.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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/* ----------------------------
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* driver parameters
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* ----------------------------
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*/
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#define DRIVER_NAME "axis_fifo"
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#define READ_BUF_SIZE 128U /* read buffer length in words */
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#define WRITE_BUF_SIZE 128U /* write buffer length in words */
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/* ----------------------------
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* IP register offsets
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* ----------------------------
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*/
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#define XLLF_ISR_OFFSET 0x00000000 /* Interrupt Status */
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#define XLLF_IER_OFFSET 0x00000004 /* Interrupt Enable */
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#define XLLF_TDFR_OFFSET 0x00000008 /* Transmit Reset */
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#define XLLF_TDFV_OFFSET 0x0000000c /* Transmit Vacancy */
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#define XLLF_TDFD_OFFSET 0x00000010 /* Transmit Data */
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#define XLLF_TLR_OFFSET 0x00000014 /* Transmit Length */
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#define XLLF_RDFR_OFFSET 0x00000018 /* Receive Reset */
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#define XLLF_RDFO_OFFSET 0x0000001c /* Receive Occupancy */
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#define XLLF_RDFD_OFFSET 0x00000020 /* Receive Data */
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#define XLLF_RLR_OFFSET 0x00000024 /* Receive Length */
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#define XLLF_SRR_OFFSET 0x00000028 /* Local Link Reset */
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#define XLLF_TDR_OFFSET 0x0000002C /* Transmit Destination */
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#define XLLF_RDR_OFFSET 0x00000030 /* Receive Destination */
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/* ----------------------------
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* reset register masks
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* ----------------------------
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*/
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#define XLLF_RDFR_RESET_MASK 0x000000a5 /* receive reset value */
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#define XLLF_TDFR_RESET_MASK 0x000000a5 /* Transmit reset value */
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#define XLLF_SRR_RESET_MASK 0x000000a5 /* Local Link reset value */
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/* ----------------------------
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* interrupt masks
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* ----------------------------
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*/
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#define XLLF_INT_RPURE_MASK 0x80000000 /* Receive under-read */
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#define XLLF_INT_RPORE_MASK 0x40000000 /* Receive over-read */
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#define XLLF_INT_RPUE_MASK 0x20000000 /* Receive underrun (empty) */
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#define XLLF_INT_TPOE_MASK 0x10000000 /* Transmit overrun */
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#define XLLF_INT_TC_MASK 0x08000000 /* Transmit complete */
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#define XLLF_INT_RC_MASK 0x04000000 /* Receive complete */
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#define XLLF_INT_TSE_MASK 0x02000000 /* Transmit length mismatch */
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#define XLLF_INT_TRC_MASK 0x01000000 /* Transmit reset complete */
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#define XLLF_INT_RRC_MASK 0x00800000 /* Receive reset complete */
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#define XLLF_INT_TFPF_MASK 0x00400000 /* Tx FIFO Programmable Full */
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#define XLLF_INT_TFPE_MASK 0x00200000 /* Tx FIFO Programmable Empty */
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#define XLLF_INT_RFPF_MASK 0x00100000 /* Rx FIFO Programmable Full */
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#define XLLF_INT_RFPE_MASK 0x00080000 /* Rx FIFO Programmable Empty */
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#define XLLF_INT_ALL_MASK 0xfff80000 /* All the ints */
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#define XLLF_INT_ERROR_MASK 0xf2000000 /* Error status ints */
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#define XLLF_INT_RXERROR_MASK 0xe0000000 /* Receive Error status ints */
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#define XLLF_INT_TXERROR_MASK 0x12000000 /* Transmit Error status ints */
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/* ----------------------------
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* globals
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* ----------------------------
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*/
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static int read_timeout = 1000; /* ms to wait before read() times out */
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static int write_timeout = 1000; /* ms to wait before write() times out */
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/* ----------------------------
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* module command-line arguments
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* ----------------------------
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*/
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module_param(read_timeout, int, 0444);
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MODULE_PARM_DESC(read_timeout, "ms to wait before blocking read() timing out; set to -1 for no timeout");
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module_param(write_timeout, int, 0444);
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MODULE_PARM_DESC(write_timeout, "ms to wait before blocking write() timing out; set to -1 for no timeout");
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/* ----------------------------
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* types
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* ----------------------------
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*/
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struct axis_fifo {
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int irq; /* interrupt */
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void __iomem *base_addr; /* kernel space memory */
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unsigned int rx_fifo_depth; /* max words in the receive fifo */
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unsigned int tx_fifo_depth; /* max words in the transmit fifo */
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int has_rx_fifo; /* whether the IP has the rx fifo enabled */
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int has_tx_fifo; /* whether the IP has the tx fifo enabled */
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wait_queue_head_t read_queue; /* wait queue for asynchronos read */
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struct mutex read_lock; /* lock for reading */
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wait_queue_head_t write_queue; /* wait queue for asynchronos write */
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struct mutex write_lock; /* lock for writing */
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unsigned int write_flags; /* write file flags */
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unsigned int read_flags; /* read file flags */
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struct device *dt_device; /* device created from the device tree */
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struct miscdevice miscdev;
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};
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/* ----------------------------
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* sysfs entries
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* ----------------------------
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*/
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static ssize_t sysfs_write(struct device *dev, const char *buf,
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size_t count, unsigned int addr_offset)
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{
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struct axis_fifo *fifo = dev_get_drvdata(dev);
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unsigned long tmp;
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int rc;
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rc = kstrtoul(buf, 0, &tmp);
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if (rc < 0)
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return rc;
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iowrite32(tmp, fifo->base_addr + addr_offset);
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return count;
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}
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static ssize_t sysfs_read(struct device *dev, char *buf,
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unsigned int addr_offset)
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{
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struct axis_fifo *fifo = dev_get_drvdata(dev);
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unsigned int read_val;
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unsigned int len;
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char tmp[32];
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read_val = ioread32(fifo->base_addr + addr_offset);
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len = snprintf(tmp, sizeof(tmp), "0x%x\n", read_val);
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memcpy(buf, tmp, len);
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return len;
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}
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static ssize_t isr_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return sysfs_write(dev, buf, count, XLLF_ISR_OFFSET);
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}
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static ssize_t isr_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sysfs_read(dev, buf, XLLF_ISR_OFFSET);
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}
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static DEVICE_ATTR_RW(isr);
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static ssize_t ier_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return sysfs_write(dev, buf, count, XLLF_IER_OFFSET);
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}
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static ssize_t ier_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sysfs_read(dev, buf, XLLF_IER_OFFSET);
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}
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static DEVICE_ATTR_RW(ier);
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static ssize_t tdfr_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return sysfs_write(dev, buf, count, XLLF_TDFR_OFFSET);
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}
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static DEVICE_ATTR_WO(tdfr);
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static ssize_t tdfv_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sysfs_read(dev, buf, XLLF_TDFV_OFFSET);
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}
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static DEVICE_ATTR_RO(tdfv);
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static ssize_t tdfd_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return sysfs_write(dev, buf, count, XLLF_TDFD_OFFSET);
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}
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static DEVICE_ATTR_WO(tdfd);
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static ssize_t tlr_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return sysfs_write(dev, buf, count, XLLF_TLR_OFFSET);
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}
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static DEVICE_ATTR_WO(tlr);
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static ssize_t rdfr_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return sysfs_write(dev, buf, count, XLLF_RDFR_OFFSET);
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}
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static DEVICE_ATTR_WO(rdfr);
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static ssize_t rdfo_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sysfs_read(dev, buf, XLLF_RDFO_OFFSET);
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}
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static DEVICE_ATTR_RO(rdfo);
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static ssize_t rdfd_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sysfs_read(dev, buf, XLLF_RDFD_OFFSET);
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}
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static DEVICE_ATTR_RO(rdfd);
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static ssize_t rlr_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sysfs_read(dev, buf, XLLF_RLR_OFFSET);
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}
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static DEVICE_ATTR_RO(rlr);
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static ssize_t srr_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return sysfs_write(dev, buf, count, XLLF_SRR_OFFSET);
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}
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static DEVICE_ATTR_WO(srr);
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static ssize_t tdr_store(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t count)
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{
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return sysfs_write(dev, buf, count, XLLF_TDR_OFFSET);
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}
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static DEVICE_ATTR_WO(tdr);
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static ssize_t rdr_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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return sysfs_read(dev, buf, XLLF_RDR_OFFSET);
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}
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static DEVICE_ATTR_RO(rdr);
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static struct attribute *axis_fifo_attrs[] = {
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&dev_attr_isr.attr,
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&dev_attr_ier.attr,
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&dev_attr_tdfr.attr,
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&dev_attr_tdfv.attr,
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&dev_attr_tdfd.attr,
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&dev_attr_tlr.attr,
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&dev_attr_rdfr.attr,
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&dev_attr_rdfo.attr,
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&dev_attr_rdfd.attr,
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&dev_attr_rlr.attr,
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&dev_attr_srr.attr,
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&dev_attr_tdr.attr,
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&dev_attr_rdr.attr,
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NULL,
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};
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static const struct attribute_group axis_fifo_attrs_group = {
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.name = "ip_registers",
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.attrs = axis_fifo_attrs,
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};
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static const struct attribute_group *axis_fifo_attrs_groups[] = {
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&axis_fifo_attrs_group,
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NULL,
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};
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/* ----------------------------
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* implementation
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* ----------------------------
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*/
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static void reset_ip_core(struct axis_fifo *fifo)
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{
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iowrite32(XLLF_SRR_RESET_MASK, fifo->base_addr + XLLF_SRR_OFFSET);
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iowrite32(XLLF_TDFR_RESET_MASK, fifo->base_addr + XLLF_TDFR_OFFSET);
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iowrite32(XLLF_RDFR_RESET_MASK, fifo->base_addr + XLLF_RDFR_OFFSET);
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iowrite32(XLLF_INT_TC_MASK | XLLF_INT_RC_MASK | XLLF_INT_RPURE_MASK |
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XLLF_INT_RPORE_MASK | XLLF_INT_RPUE_MASK |
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XLLF_INT_TPOE_MASK | XLLF_INT_TSE_MASK,
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fifo->base_addr + XLLF_IER_OFFSET);
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iowrite32(XLLF_INT_ALL_MASK, fifo->base_addr + XLLF_ISR_OFFSET);
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}
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/**
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* axis_fifo_read() - Read a packet from AXIS-FIFO character device.
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* @f: Open file.
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* @buf: User space buffer to read to.
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* @len: User space buffer length.
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* @off: Buffer offset.
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*
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* As defined by the device's documentation, we need to check the device's
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* occupancy before reading the length register and then the data. All these
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* operations must be executed atomically, in order and one after the other
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* without missing any.
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*
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* Returns the number of bytes read from the device or negative error code
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* on failure.
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*/
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static ssize_t axis_fifo_read(struct file *f, char __user *buf,
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size_t len, loff_t *off)
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{
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struct axis_fifo *fifo = (struct axis_fifo *)f->private_data;
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size_t bytes_available;
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unsigned int words_available;
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unsigned int copied;
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unsigned int copy;
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unsigned int i;
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int ret;
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u32 tmp_buf[READ_BUF_SIZE];
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if (fifo->read_flags & O_NONBLOCK) {
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/*
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* Device opened in non-blocking mode. Try to lock it and then
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* check if any packet is available.
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*/
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if (!mutex_trylock(&fifo->read_lock))
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return -EAGAIN;
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if (!ioread32(fifo->base_addr + XLLF_RDFO_OFFSET)) {
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ret = -EAGAIN;
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goto end_unlock;
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}
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} else {
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/* opened in blocking mode
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* wait for a packet available interrupt (or timeout)
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* if nothing is currently available
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*/
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mutex_lock(&fifo->read_lock);
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ret = wait_event_interruptible_timeout(fifo->read_queue,
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ioread32(fifo->base_addr + XLLF_RDFO_OFFSET),
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(read_timeout >= 0) ?
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msecs_to_jiffies(read_timeout) :
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MAX_SCHEDULE_TIMEOUT);
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if (ret <= 0) {
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if (ret == 0) {
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ret = -EAGAIN;
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} else if (ret != -ERESTARTSYS) {
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dev_err(fifo->dt_device, "wait_event_interruptible_timeout() error in read (ret=%i)\n",
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ret);
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}
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goto end_unlock;
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}
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}
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bytes_available = ioread32(fifo->base_addr + XLLF_RLR_OFFSET);
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if (!bytes_available) {
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dev_err(fifo->dt_device, "received a packet of length 0 - fifo core will be reset\n");
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reset_ip_core(fifo);
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ret = -EIO;
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goto end_unlock;
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}
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if (bytes_available > len) {
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dev_err(fifo->dt_device, "user read buffer too small (available bytes=%zu user buffer bytes=%zu) - fifo core will be reset\n",
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bytes_available, len);
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reset_ip_core(fifo);
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ret = -EINVAL;
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goto end_unlock;
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}
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if (bytes_available % sizeof(u32)) {
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/* this probably can't happen unless IP
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* registers were previously mishandled
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*/
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dev_err(fifo->dt_device, "received a packet that isn't word-aligned - fifo core will be reset\n");
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reset_ip_core(fifo);
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ret = -EIO;
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goto end_unlock;
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}
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words_available = bytes_available / sizeof(u32);
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/* read data into an intermediate buffer, copying the contents
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* to userspace when the buffer is full
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*/
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copied = 0;
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while (words_available > 0) {
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copy = min(words_available, READ_BUF_SIZE);
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for (i = 0; i < copy; i++) {
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tmp_buf[i] = ioread32(fifo->base_addr +
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XLLF_RDFD_OFFSET);
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}
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if (copy_to_user(buf + copied * sizeof(u32), tmp_buf,
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copy * sizeof(u32))) {
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reset_ip_core(fifo);
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ret = -EFAULT;
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goto end_unlock;
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}
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copied += copy;
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words_available -= copy;
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}
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ret = bytes_available;
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end_unlock:
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mutex_unlock(&fifo->read_lock);
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return ret;
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}
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/**
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* axis_fifo_write() - Write buffer to AXIS-FIFO character device.
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* @f: Open file.
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* @buf: User space buffer to write to the device.
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* @len: User space buffer length.
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* @off: Buffer offset.
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*
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* As defined by the device's documentation, we need to write to the device's
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* data buffer then to the device's packet length register atomically. Also,
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* we need to lock before checking if the device has available space to avoid
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* any concurrency issue.
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*
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* Returns the number of bytes written to the device or negative error code
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* on failure.
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*/
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static ssize_t axis_fifo_write(struct file *f, const char __user *buf,
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size_t len, loff_t *off)
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{
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struct axis_fifo *fifo = (struct axis_fifo *)f->private_data;
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unsigned int words_to_write;
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unsigned int copied;
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unsigned int copy;
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unsigned int i;
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int ret;
|
|
u32 tmp_buf[WRITE_BUF_SIZE];
|
|
|
|
if (len % sizeof(u32)) {
|
|
dev_err(fifo->dt_device,
|
|
"tried to send a packet that isn't word-aligned\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
words_to_write = len / sizeof(u32);
|
|
|
|
if (!words_to_write) {
|
|
dev_err(fifo->dt_device,
|
|
"tried to send a packet of length 0\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (words_to_write > fifo->tx_fifo_depth) {
|
|
dev_err(fifo->dt_device, "tried to write more words [%u] than slots in the fifo buffer [%u]\n",
|
|
words_to_write, fifo->tx_fifo_depth);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (fifo->write_flags & O_NONBLOCK) {
|
|
/*
|
|
* Device opened in non-blocking mode. Try to lock it and then
|
|
* check if there is any room to write the given buffer.
|
|
*/
|
|
if (!mutex_trylock(&fifo->write_lock))
|
|
return -EAGAIN;
|
|
|
|
if (words_to_write > ioread32(fifo->base_addr +
|
|
XLLF_TDFV_OFFSET)) {
|
|
ret = -EAGAIN;
|
|
goto end_unlock;
|
|
}
|
|
} else {
|
|
/* opened in blocking mode */
|
|
|
|
/* wait for an interrupt (or timeout) if there isn't
|
|
* currently enough room in the fifo
|
|
*/
|
|
mutex_lock(&fifo->write_lock);
|
|
ret = wait_event_interruptible_timeout(fifo->write_queue,
|
|
ioread32(fifo->base_addr + XLLF_TDFV_OFFSET)
|
|
>= words_to_write,
|
|
(write_timeout >= 0) ?
|
|
msecs_to_jiffies(write_timeout) :
|
|
MAX_SCHEDULE_TIMEOUT);
|
|
|
|
if (ret <= 0) {
|
|
if (ret == 0) {
|
|
ret = -EAGAIN;
|
|
} else if (ret != -ERESTARTSYS) {
|
|
dev_err(fifo->dt_device, "wait_event_interruptible_timeout() error in write (ret=%i)\n",
|
|
ret);
|
|
}
|
|
|
|
goto end_unlock;
|
|
}
|
|
}
|
|
|
|
/* write data from an intermediate buffer into the fifo IP, refilling
|
|
* the buffer with userspace data as needed
|
|
*/
|
|
copied = 0;
|
|
while (words_to_write > 0) {
|
|
copy = min(words_to_write, WRITE_BUF_SIZE);
|
|
|
|
if (copy_from_user(tmp_buf, buf + copied * sizeof(u32),
|
|
copy * sizeof(u32))) {
|
|
reset_ip_core(fifo);
|
|
ret = -EFAULT;
|
|
goto end_unlock;
|
|
}
|
|
|
|
for (i = 0; i < copy; i++)
|
|
iowrite32(tmp_buf[i], fifo->base_addr +
|
|
XLLF_TDFD_OFFSET);
|
|
|
|
copied += copy;
|
|
words_to_write -= copy;
|
|
}
|
|
|
|
ret = copied * sizeof(u32);
|
|
|
|
/* write packet size to fifo */
|
|
iowrite32(ret, fifo->base_addr + XLLF_TLR_OFFSET);
|
|
|
|
end_unlock:
|
|
mutex_unlock(&fifo->write_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static irqreturn_t axis_fifo_irq(int irq, void *dw)
|
|
{
|
|
struct axis_fifo *fifo = (struct axis_fifo *)dw;
|
|
unsigned int pending_interrupts;
|
|
|
|
do {
|
|
pending_interrupts = ioread32(fifo->base_addr +
|
|
XLLF_IER_OFFSET) &
|
|
ioread32(fifo->base_addr
|
|
+ XLLF_ISR_OFFSET);
|
|
if (pending_interrupts & XLLF_INT_RC_MASK) {
|
|
/* packet received */
|
|
|
|
/* wake the reader process if it is waiting */
|
|
wake_up(&fifo->read_queue);
|
|
|
|
/* clear interrupt */
|
|
iowrite32(XLLF_INT_RC_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_TC_MASK) {
|
|
/* packet sent */
|
|
|
|
/* wake the writer process if it is waiting */
|
|
wake_up(&fifo->write_queue);
|
|
|
|
iowrite32(XLLF_INT_TC_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_TFPF_MASK) {
|
|
/* transmit fifo programmable full */
|
|
|
|
iowrite32(XLLF_INT_TFPF_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_TFPE_MASK) {
|
|
/* transmit fifo programmable empty */
|
|
|
|
iowrite32(XLLF_INT_TFPE_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_RFPF_MASK) {
|
|
/* receive fifo programmable full */
|
|
|
|
iowrite32(XLLF_INT_RFPF_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_RFPE_MASK) {
|
|
/* receive fifo programmable empty */
|
|
|
|
iowrite32(XLLF_INT_RFPE_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_TRC_MASK) {
|
|
/* transmit reset complete interrupt */
|
|
|
|
iowrite32(XLLF_INT_TRC_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_RRC_MASK) {
|
|
/* receive reset complete interrupt */
|
|
|
|
iowrite32(XLLF_INT_RRC_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_RPURE_MASK) {
|
|
/* receive fifo under-read error interrupt */
|
|
dev_err(fifo->dt_device,
|
|
"receive under-read interrupt\n");
|
|
|
|
iowrite32(XLLF_INT_RPURE_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_RPORE_MASK) {
|
|
/* receive over-read error interrupt */
|
|
dev_err(fifo->dt_device,
|
|
"receive over-read interrupt\n");
|
|
|
|
iowrite32(XLLF_INT_RPORE_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_RPUE_MASK) {
|
|
/* receive underrun error interrupt */
|
|
dev_err(fifo->dt_device,
|
|
"receive underrun error interrupt\n");
|
|
|
|
iowrite32(XLLF_INT_RPUE_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_TPOE_MASK) {
|
|
/* transmit overrun error interrupt */
|
|
dev_err(fifo->dt_device,
|
|
"transmit overrun error interrupt\n");
|
|
|
|
iowrite32(XLLF_INT_TPOE_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts & XLLF_INT_TSE_MASK) {
|
|
/* transmit length mismatch error interrupt */
|
|
dev_err(fifo->dt_device,
|
|
"transmit length mismatch error interrupt\n");
|
|
|
|
iowrite32(XLLF_INT_TSE_MASK & XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
} else if (pending_interrupts) {
|
|
/* unknown interrupt type */
|
|
dev_err(fifo->dt_device,
|
|
"unknown interrupt(s) 0x%x\n",
|
|
pending_interrupts);
|
|
|
|
iowrite32(XLLF_INT_ALL_MASK,
|
|
fifo->base_addr + XLLF_ISR_OFFSET);
|
|
}
|
|
} while (pending_interrupts);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int axis_fifo_open(struct inode *inod, struct file *f)
|
|
{
|
|
struct axis_fifo *fifo = container_of(f->private_data,
|
|
struct axis_fifo, miscdev);
|
|
f->private_data = fifo;
|
|
|
|
if (((f->f_flags & O_ACCMODE) == O_WRONLY) ||
|
|
((f->f_flags & O_ACCMODE) == O_RDWR)) {
|
|
if (fifo->has_tx_fifo) {
|
|
fifo->write_flags = f->f_flags;
|
|
} else {
|
|
dev_err(fifo->dt_device, "tried to open device for write but the transmit fifo is disabled\n");
|
|
return -EPERM;
|
|
}
|
|
}
|
|
|
|
if (((f->f_flags & O_ACCMODE) == O_RDONLY) ||
|
|
((f->f_flags & O_ACCMODE) == O_RDWR)) {
|
|
if (fifo->has_rx_fifo) {
|
|
fifo->read_flags = f->f_flags;
|
|
} else {
|
|
dev_err(fifo->dt_device, "tried to open device for read but the receive fifo is disabled\n");
|
|
return -EPERM;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int axis_fifo_close(struct inode *inod, struct file *f)
|
|
{
|
|
f->private_data = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct file_operations fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = axis_fifo_open,
|
|
.release = axis_fifo_close,
|
|
.read = axis_fifo_read,
|
|
.write = axis_fifo_write
|
|
};
|
|
|
|
/* read named property from the device tree */
|
|
static int get_dts_property(struct axis_fifo *fifo,
|
|
char *name, unsigned int *var)
|
|
{
|
|
int rc;
|
|
|
|
rc = of_property_read_u32(fifo->dt_device->of_node, name, var);
|
|
if (rc) {
|
|
dev_err(fifo->dt_device, "couldn't read IP dts property '%s'",
|
|
name);
|
|
return rc;
|
|
}
|
|
dev_dbg(fifo->dt_device, "dts property '%s' = %u\n",
|
|
name, *var);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int axis_fifo_parse_dt(struct axis_fifo *fifo)
|
|
{
|
|
int ret;
|
|
unsigned int value;
|
|
|
|
ret = get_dts_property(fifo, "xlnx,axi-str-rxd-tdata-width", &value);
|
|
if (ret) {
|
|
dev_err(fifo->dt_device, "missing xlnx,axi-str-rxd-tdata-width property\n");
|
|
goto end;
|
|
} else if (value != 32) {
|
|
dev_err(fifo->dt_device, "xlnx,axi-str-rxd-tdata-width only supports 32 bits\n");
|
|
ret = -EIO;
|
|
goto end;
|
|
}
|
|
|
|
ret = get_dts_property(fifo, "xlnx,axi-str-txd-tdata-width", &value);
|
|
if (ret) {
|
|
dev_err(fifo->dt_device, "missing xlnx,axi-str-txd-tdata-width property\n");
|
|
goto end;
|
|
} else if (value != 32) {
|
|
dev_err(fifo->dt_device, "xlnx,axi-str-txd-tdata-width only supports 32 bits\n");
|
|
ret = -EIO;
|
|
goto end;
|
|
}
|
|
|
|
ret = get_dts_property(fifo, "xlnx,rx-fifo-depth",
|
|
&fifo->rx_fifo_depth);
|
|
if (ret) {
|
|
dev_err(fifo->dt_device, "missing xlnx,rx-fifo-depth property\n");
|
|
ret = -EIO;
|
|
goto end;
|
|
}
|
|
|
|
ret = get_dts_property(fifo, "xlnx,tx-fifo-depth",
|
|
&fifo->tx_fifo_depth);
|
|
if (ret) {
|
|
dev_err(fifo->dt_device, "missing xlnx,tx-fifo-depth property\n");
|
|
ret = -EIO;
|
|
goto end;
|
|
}
|
|
|
|
/* IP sets TDFV to fifo depth - 4 so we will do the same */
|
|
fifo->tx_fifo_depth -= 4;
|
|
|
|
ret = get_dts_property(fifo, "xlnx,use-rx-data", &fifo->has_rx_fifo);
|
|
if (ret) {
|
|
dev_err(fifo->dt_device, "missing xlnx,use-rx-data property\n");
|
|
ret = -EIO;
|
|
goto end;
|
|
}
|
|
|
|
ret = get_dts_property(fifo, "xlnx,use-tx-data", &fifo->has_tx_fifo);
|
|
if (ret) {
|
|
dev_err(fifo->dt_device, "missing xlnx,use-tx-data property\n");
|
|
ret = -EIO;
|
|
goto end;
|
|
}
|
|
|
|
end:
|
|
return ret;
|
|
}
|
|
|
|
static int axis_fifo_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *r_mem; /* IO mem resources */
|
|
struct device *dev = &pdev->dev; /* OS device (from device tree) */
|
|
struct axis_fifo *fifo = NULL;
|
|
char *device_name;
|
|
int rc = 0; /* error return value */
|
|
|
|
/* ----------------------------
|
|
* init wrapper device
|
|
* ----------------------------
|
|
*/
|
|
|
|
device_name = devm_kzalloc(dev, 32, GFP_KERNEL);
|
|
if (!device_name)
|
|
return -ENOMEM;
|
|
|
|
/* allocate device wrapper memory */
|
|
fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
|
|
if (!fifo)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(dev, fifo);
|
|
fifo->dt_device = dev;
|
|
|
|
init_waitqueue_head(&fifo->read_queue);
|
|
init_waitqueue_head(&fifo->write_queue);
|
|
|
|
mutex_init(&fifo->read_lock);
|
|
mutex_init(&fifo->write_lock);
|
|
|
|
/* ----------------------------
|
|
* init device memory space
|
|
* ----------------------------
|
|
*/
|
|
|
|
/* get iospace for the device */
|
|
r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!r_mem) {
|
|
dev_err(fifo->dt_device, "invalid address\n");
|
|
rc = -ENODEV;
|
|
goto err_initial;
|
|
}
|
|
|
|
/* request physical memory */
|
|
fifo->base_addr = devm_ioremap_resource(fifo->dt_device, r_mem);
|
|
if (IS_ERR(fifo->base_addr)) {
|
|
rc = PTR_ERR(fifo->base_addr);
|
|
goto err_initial;
|
|
}
|
|
|
|
dev_dbg(fifo->dt_device, "remapped memory to 0x%p\n", fifo->base_addr);
|
|
|
|
/* create unique device name */
|
|
snprintf(device_name, 32, "%s_%pa", DRIVER_NAME, &r_mem->start);
|
|
dev_dbg(fifo->dt_device, "device name [%s]\n", device_name);
|
|
|
|
/* ----------------------------
|
|
* init IP
|
|
* ----------------------------
|
|
*/
|
|
|
|
rc = axis_fifo_parse_dt(fifo);
|
|
if (rc)
|
|
goto err_initial;
|
|
|
|
reset_ip_core(fifo);
|
|
|
|
/* ----------------------------
|
|
* init device interrupts
|
|
* ----------------------------
|
|
*/
|
|
|
|
/* get IRQ resource */
|
|
rc = platform_get_irq(pdev, 0);
|
|
if (rc < 0)
|
|
goto err_initial;
|
|
|
|
/* request IRQ */
|
|
fifo->irq = rc;
|
|
rc = devm_request_irq(fifo->dt_device, fifo->irq, &axis_fifo_irq, 0,
|
|
DRIVER_NAME, fifo);
|
|
if (rc) {
|
|
dev_err(fifo->dt_device, "couldn't allocate interrupt %i\n",
|
|
fifo->irq);
|
|
goto err_initial;
|
|
}
|
|
|
|
/* ----------------------------
|
|
* init char device
|
|
* ----------------------------
|
|
*/
|
|
|
|
/* create character device */
|
|
fifo->miscdev.fops = &fops;
|
|
fifo->miscdev.minor = MISC_DYNAMIC_MINOR;
|
|
fifo->miscdev.name = device_name;
|
|
fifo->miscdev.groups = axis_fifo_attrs_groups;
|
|
fifo->miscdev.parent = dev;
|
|
rc = misc_register(&fifo->miscdev);
|
|
if (rc < 0)
|
|
goto err_initial;
|
|
|
|
dev_info(fifo->dt_device, "axis-fifo created at %pa mapped to 0x%pa, irq=%i\n",
|
|
&r_mem->start, &fifo->base_addr, fifo->irq);
|
|
|
|
return 0;
|
|
|
|
err_initial:
|
|
dev_set_drvdata(dev, NULL);
|
|
return rc;
|
|
}
|
|
|
|
static int axis_fifo_remove(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct axis_fifo *fifo = dev_get_drvdata(dev);
|
|
|
|
misc_deregister(&fifo->miscdev);
|
|
dev_set_drvdata(dev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id axis_fifo_of_match[] = {
|
|
{ .compatible = "xlnx,axi-fifo-mm-s-4.1", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, axis_fifo_of_match);
|
|
|
|
static struct platform_driver axis_fifo_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = axis_fifo_of_match,
|
|
},
|
|
.probe = axis_fifo_probe,
|
|
.remove = axis_fifo_remove,
|
|
};
|
|
|
|
static int __init axis_fifo_init(void)
|
|
{
|
|
pr_info("axis-fifo driver loaded with parameters read_timeout = %i, write_timeout = %i\n",
|
|
read_timeout, write_timeout);
|
|
return platform_driver_register(&axis_fifo_driver);
|
|
}
|
|
|
|
module_init(axis_fifo_init);
|
|
|
|
static void __exit axis_fifo_exit(void)
|
|
{
|
|
platform_driver_unregister(&axis_fifo_driver);
|
|
}
|
|
|
|
module_exit(axis_fifo_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Jacob Feder <jacobsfeder@gmail.com>");
|
|
MODULE_DESCRIPTION("Xilinx AXI-Stream FIFO v4.1 IP core driver");
|