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![Andy Shevchenko](/assets/img/avatar_default.png)
Himax HX8347d has non-standard register to control orientation. Add support for different orientation values. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210503172114.27891-4-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
183 lines
4.6 KiB
C
183 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* FB driver for the HX8347D LCD Controller
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*
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* Copyright (C) 2013 Christian Vogelgsang
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*
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* Based on driver code found here: https://github.com/watterott/r61505u-Adapter
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include "fbtft.h"
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#define DRVNAME "fb_hx8347d"
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#define WIDTH 320
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#define HEIGHT 240
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#define DEFAULT_GAMMA "0 0 0 0 0 0 0 0 0 0 0 0 0 0\n" \
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"0 0 0 0 0 0 0 0 0 0 0 0 0 0"
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static int init_display(struct fbtft_par *par)
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{
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par->fbtftops.reset(par);
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/* driving ability */
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write_reg(par, 0xEA, 0x00);
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write_reg(par, 0xEB, 0x20);
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write_reg(par, 0xEC, 0x0C);
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write_reg(par, 0xED, 0xC4);
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write_reg(par, 0xE8, 0x40);
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write_reg(par, 0xE9, 0x38);
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write_reg(par, 0xF1, 0x01);
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write_reg(par, 0xF2, 0x10);
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write_reg(par, 0x27, 0xA3);
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/* power voltage */
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write_reg(par, 0x1B, 0x1B);
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write_reg(par, 0x1A, 0x01);
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write_reg(par, 0x24, 0x2F);
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write_reg(par, 0x25, 0x57);
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/* VCOM offset */
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write_reg(par, 0x23, 0x8D); /* for flicker adjust */
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/* power on */
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write_reg(par, 0x18, 0x36);
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write_reg(par, 0x19, 0x01); /* start osc */
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write_reg(par, 0x01, 0x00); /* wakeup */
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write_reg(par, 0x1F, 0x88);
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mdelay(5);
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write_reg(par, 0x1F, 0x80);
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mdelay(5);
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write_reg(par, 0x1F, 0x90);
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mdelay(5);
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write_reg(par, 0x1F, 0xD0);
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mdelay(5);
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/* color selection */
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write_reg(par, 0x17, 0x05); /* 65k */
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/*panel characteristic */
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write_reg(par, 0x36, 0x00);
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/*display on */
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write_reg(par, 0x28, 0x38);
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mdelay(40);
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write_reg(par, 0x28, 0x3C);
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return 0;
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}
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static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
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{
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write_reg(par, 0x02, (xs >> 8) & 0xFF);
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write_reg(par, 0x03, xs & 0xFF);
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write_reg(par, 0x04, (xe >> 8) & 0xFF);
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write_reg(par, 0x05, xe & 0xFF);
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write_reg(par, 0x06, (ys >> 8) & 0xFF);
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write_reg(par, 0x07, ys & 0xFF);
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write_reg(par, 0x08, (ye >> 8) & 0xFF);
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write_reg(par, 0x09, ye & 0xFF);
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write_reg(par, 0x22);
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}
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#define MEM_Y BIT(7) /* MY row address order */
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#define MEM_X BIT(6) /* MX column address order */
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#define MEM_V BIT(5) /* MV row / column exchange */
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#define MEM_L BIT(4) /* ML vertical refresh order */
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#define MEM_BGR (3) /* RGB-BGR Order */
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static int set_var(struct fbtft_par *par)
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{
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switch (par->info->var.rotate) {
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case 0:
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write_reg(par, 0x16, MEM_V | MEM_X | (par->bgr << MEM_BGR));
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break;
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case 270:
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write_reg(par, 0x16, par->bgr << MEM_BGR);
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break;
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case 180:
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write_reg(par, 0x16, MEM_V | MEM_Y | (par->bgr << MEM_BGR));
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break;
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case 90:
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write_reg(par, 0x16, MEM_X | MEM_Y | (par->bgr << MEM_BGR));
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break;
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}
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return 0;
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}
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/*
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* Gamma string format:
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* VRP0 VRP1 VRP2 VRP3 VRP4 VRP5 PRP0 PRP1 PKP0 PKP1 PKP2 PKP3 PKP4 CGM
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* VRN0 VRN1 VRN2 VRN3 VRN4 VRN5 PRN0 PRN1 PKN0 PKN1 PKN2 PKN3 PKN4 CGM
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*/
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#define CURVE(num, idx) curves[(num) * par->gamma.num_values + (idx)]
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static int set_gamma(struct fbtft_par *par, u32 *curves)
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{
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static const unsigned long mask[] = {
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0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x7f, 0x7f, 0x1f, 0x1f,
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0x1f, 0x1f, 0x1f, 0x0f,
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};
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int i, j;
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int acc = 0;
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/* apply mask */
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for (i = 0; i < par->gamma.num_curves; i++)
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for (j = 0; j < par->gamma.num_values; j++) {
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acc += CURVE(i, j);
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CURVE(i, j) &= mask[j];
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}
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if (acc == 0) /* skip if all values are zero */
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return 0;
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for (i = 0; i < par->gamma.num_curves; i++) {
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write_reg(par, 0x40 + (i * 0x10), CURVE(i, 0));
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write_reg(par, 0x41 + (i * 0x10), CURVE(i, 1));
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write_reg(par, 0x42 + (i * 0x10), CURVE(i, 2));
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write_reg(par, 0x43 + (i * 0x10), CURVE(i, 3));
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write_reg(par, 0x44 + (i * 0x10), CURVE(i, 4));
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write_reg(par, 0x45 + (i * 0x10), CURVE(i, 5));
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write_reg(par, 0x46 + (i * 0x10), CURVE(i, 6));
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write_reg(par, 0x47 + (i * 0x10), CURVE(i, 7));
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write_reg(par, 0x48 + (i * 0x10), CURVE(i, 8));
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write_reg(par, 0x49 + (i * 0x10), CURVE(i, 9));
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write_reg(par, 0x4A + (i * 0x10), CURVE(i, 10));
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write_reg(par, 0x4B + (i * 0x10), CURVE(i, 11));
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write_reg(par, 0x4C + (i * 0x10), CURVE(i, 12));
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}
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write_reg(par, 0x5D, (CURVE(1, 0) << 4) | CURVE(0, 0));
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return 0;
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}
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#undef CURVE
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static struct fbtft_display display = {
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.regwidth = 8,
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.width = WIDTH,
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.height = HEIGHT,
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.gamma_num = 2,
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.gamma_len = 14,
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.gamma = DEFAULT_GAMMA,
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.fbtftops = {
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.init_display = init_display,
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.set_addr_win = set_addr_win,
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.set_var = set_var,
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.set_gamma = set_gamma,
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},
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};
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FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8347d", &display);
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MODULE_ALIAS("spi:" DRVNAME);
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MODULE_ALIAS("platform:" DRVNAME);
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MODULE_ALIAS("spi:hx8347d");
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MODULE_ALIAS("platform:hx8347d");
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MODULE_DESCRIPTION("FB driver for the HX8347D LCD Controller");
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MODULE_AUTHOR("Christian Vogelgsang");
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MODULE_LICENSE("GPL");
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