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![Oliver Graute](/assets/img/avatar_default.png)
In rare cases the display is flipped or mirrored. This was observed more
often in a low temperature environment. A clean reset on init_display()
should help to get registers in a sane state.
Fixes: ef8f317795
(staging: fbtft: use init function instead of init sequence)
Cc: stable@vger.kernel.org
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Link: https://lore.kernel.org/r/20220210085322.15676-1-oliver.graute@kococonnector.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
394 lines
9.1 KiB
C
394 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* FB driver for the ST7789V LCD Controller
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*
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* Copyright (C) 2015 Dennis Menschel
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/completion.h>
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#include <linux/module.h>
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#include <video/mipi_display.h>
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#include "fbtft.h"
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#define DRVNAME "fb_st7789v"
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#define DEFAULT_GAMMA \
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"70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25\n" \
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"70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25"
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#define HSD20_IPS_GAMMA \
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"D0 05 0A 09 08 05 2E 44 45 0F 17 16 2B 33\n" \
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"D0 05 0A 09 08 05 2E 43 45 0F 16 16 2B 33"
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#define HSD20_IPS 1
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/**
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* enum st7789v_command - ST7789V display controller commands
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*
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* @PORCTRL: porch setting
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* @GCTRL: gate control
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* @VCOMS: VCOM setting
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* @VDVVRHEN: VDV and VRH command enable
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* @VRHS: VRH set
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* @VDVS: VDV set
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* @VCMOFSET: VCOM offset set
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* @PWCTRL1: power control 1
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* @PVGAMCTRL: positive voltage gamma control
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* @NVGAMCTRL: negative voltage gamma control
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*
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* The command names are the same as those found in the datasheet to ease
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* looking up their semantics and usage.
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*
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* Note that the ST7789V display controller offers quite a few more commands
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* which have been omitted from this list as they are not used at the moment.
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* Furthermore, commands that are compliant with the MIPI DCS have been left
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* out as well to avoid duplicate entries.
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*/
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enum st7789v_command {
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PORCTRL = 0xB2,
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GCTRL = 0xB7,
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VCOMS = 0xBB,
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VDVVRHEN = 0xC2,
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VRHS = 0xC3,
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VDVS = 0xC4,
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VCMOFSET = 0xC5,
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PWCTRL1 = 0xD0,
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PVGAMCTRL = 0xE0,
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NVGAMCTRL = 0xE1,
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};
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#define MADCTL_BGR BIT(3) /* bitmask for RGB/BGR order */
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#define MADCTL_MV BIT(5) /* bitmask for page/column order */
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#define MADCTL_MX BIT(6) /* bitmask for column address order */
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#define MADCTL_MY BIT(7) /* bitmask for page address order */
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/* 60Hz for 16.6ms, configured as 2*16.6ms */
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#define PANEL_TE_TIMEOUT_MS 33
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static struct completion panel_te; /* completion for panel TE line */
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static int irq_te; /* Linux IRQ for LCD TE line */
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static irqreturn_t panel_te_handler(int irq, void *data)
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{
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complete(&panel_te);
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return IRQ_HANDLED;
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}
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/*
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* init_tearing_effect_line() - init tearing effect line.
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* @par: FBTFT parameter object.
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*
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* Return: 0 on success, or a negative error code otherwise.
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*/
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static int init_tearing_effect_line(struct fbtft_par *par)
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{
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struct device *dev = par->info->device;
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struct gpio_desc *te;
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int rc, irq;
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te = gpiod_get_optional(dev, "te", GPIOD_IN);
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if (IS_ERR(te))
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return dev_err_probe(dev, PTR_ERR(te), "Failed to request te GPIO\n");
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/* if te is NULL, indicating no configuration, directly return success */
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if (!te) {
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irq_te = 0;
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return 0;
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}
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irq = gpiod_to_irq(te);
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/* GPIO is locked as an IRQ, we may drop the reference */
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gpiod_put(te);
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if (irq < 0)
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return irq;
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irq_te = irq;
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init_completion(&panel_te);
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/* The effective state is high and lasts no more than 1000 microseconds */
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rc = devm_request_irq(dev, irq_te, panel_te_handler,
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IRQF_TRIGGER_RISING, "TE_GPIO", par);
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if (rc)
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return dev_err_probe(dev, rc, "TE IRQ request failed.\n");
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disable_irq_nosync(irq_te);
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return 0;
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}
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/**
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* init_display() - initialize the display controller
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*
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* @par: FBTFT parameter object
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*
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* Most of the commands in this init function set their parameters to the
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* same default values which are already in place after the display has been
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* powered up. (The main exception to this rule is the pixel format which
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* would default to 18 instead of 16 bit per pixel.)
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* Nonetheless, this sequence can be used as a template for concrete
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* displays which usually need some adjustments.
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*
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* Return: 0 on success, < 0 if error occurred.
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*/
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static int init_display(struct fbtft_par *par)
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{
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int rc;
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par->fbtftops.reset(par);
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rc = init_tearing_effect_line(par);
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if (rc)
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return rc;
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/* turn off sleep mode */
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write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
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mdelay(120);
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/* set pixel format to RGB-565 */
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write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
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if (HSD20_IPS)
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write_reg(par, PORCTRL, 0x05, 0x05, 0x00, 0x33, 0x33);
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else
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write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22);
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/*
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* VGH = 13.26V
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* VGL = -10.43V
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*/
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if (HSD20_IPS)
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write_reg(par, GCTRL, 0x75);
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else
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write_reg(par, GCTRL, 0x35);
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/*
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* VDV and VRH register values come from command write
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* (instead of NVM)
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*/
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write_reg(par, VDVVRHEN, 0x01, 0xFF);
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/*
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* VAP = 4.1V + (VCOM + VCOM offset + 0.5 * VDV)
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* VAN = -4.1V + (VCOM + VCOM offset + 0.5 * VDV)
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*/
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if (HSD20_IPS)
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write_reg(par, VRHS, 0x13);
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else
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write_reg(par, VRHS, 0x0B);
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/* VDV = 0V */
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write_reg(par, VDVS, 0x20);
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/* VCOM = 0.9V */
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if (HSD20_IPS)
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write_reg(par, VCOMS, 0x22);
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else
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write_reg(par, VCOMS, 0x20);
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/* VCOM offset = 0V */
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write_reg(par, VCMOFSET, 0x20);
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/*
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* AVDD = 6.8V
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* AVCL = -4.8V
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* VDS = 2.3V
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*/
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write_reg(par, PWCTRL1, 0xA4, 0xA1);
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/* TE line output is off by default when powering on */
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if (irq_te)
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write_reg(par, MIPI_DCS_SET_TEAR_ON, 0x00);
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write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
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if (HSD20_IPS)
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write_reg(par, MIPI_DCS_ENTER_INVERT_MODE);
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return 0;
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}
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/*
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* write_vmem() - write data to display.
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* @par: FBTFT parameter object.
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* @offset: offset from screen_buffer.
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* @len: the length of data to be writte.
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*
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* Return: 0 on success, or a negative error code otherwise.
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*/
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static int write_vmem(struct fbtft_par *par, size_t offset, size_t len)
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{
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struct device *dev = par->info->device;
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int ret;
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if (irq_te) {
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enable_irq(irq_te);
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reinit_completion(&panel_te);
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ret = wait_for_completion_timeout(&panel_te,
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msecs_to_jiffies(PANEL_TE_TIMEOUT_MS));
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if (ret == 0)
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dev_err(dev, "wait panel TE timeout\n");
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disable_irq(irq_te);
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}
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switch (par->pdata->display.buswidth) {
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case 8:
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ret = fbtft_write_vmem16_bus8(par, offset, len);
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break;
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case 9:
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ret = fbtft_write_vmem16_bus9(par, offset, len);
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break;
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case 16:
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ret = fbtft_write_vmem16_bus16(par, offset, len);
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break;
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default:
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dev_err(dev, "Unsupported buswidth %d\n",
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par->pdata->display.buswidth);
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ret = 0;
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break;
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}
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return ret;
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}
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/**
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* set_var() - apply LCD properties like rotation and BGR mode
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*
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* @par: FBTFT parameter object
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*
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* Return: 0 on success, < 0 if error occurred.
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*/
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static int set_var(struct fbtft_par *par)
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{
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u8 madctl_par = 0;
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if (par->bgr)
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madctl_par |= MADCTL_BGR;
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switch (par->info->var.rotate) {
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case 0:
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break;
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case 90:
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madctl_par |= (MADCTL_MV | MADCTL_MY);
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break;
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case 180:
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madctl_par |= (MADCTL_MX | MADCTL_MY);
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break;
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case 270:
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madctl_par |= (MADCTL_MV | MADCTL_MX);
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break;
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default:
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return -EINVAL;
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}
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write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, madctl_par);
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return 0;
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}
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/**
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* set_gamma() - set gamma curves
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*
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* @par: FBTFT parameter object
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* @curves: gamma curves
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*
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* Before the gamma curves are applied, they are preprocessed with a bitmask
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* to ensure syntactically correct input for the display controller.
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* This implies that the curves input parameter might be changed by this
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* function and that illegal gamma values are auto-corrected and not
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* reported as errors.
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*
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* Return: 0 on success, < 0 if error occurred.
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*/
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static int set_gamma(struct fbtft_par *par, u32 *curves)
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{
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int i;
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int j;
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int c; /* curve index offset */
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/*
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* Bitmasks for gamma curve command parameters.
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* The masks are the same for both positive and negative voltage
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* gamma curves.
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*/
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static const u8 gamma_par_mask[] = {
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0xFF, /* V63[3:0], V0[3:0]*/
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0x3F, /* V1[5:0] */
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0x3F, /* V2[5:0] */
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0x1F, /* V4[4:0] */
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0x1F, /* V6[4:0] */
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0x3F, /* J0[1:0], V13[3:0] */
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0x7F, /* V20[6:0] */
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0x77, /* V36[2:0], V27[2:0] */
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0x7F, /* V43[6:0] */
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0x3F, /* J1[1:0], V50[3:0] */
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0x1F, /* V57[4:0] */
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0x1F, /* V59[4:0] */
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0x3F, /* V61[5:0] */
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0x3F, /* V62[5:0] */
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};
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for (i = 0; i < par->gamma.num_curves; i++) {
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c = i * par->gamma.num_values;
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for (j = 0; j < par->gamma.num_values; j++)
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curves[c + j] &= gamma_par_mask[j];
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write_reg(par, PVGAMCTRL + i,
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curves[c + 0], curves[c + 1], curves[c + 2],
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curves[c + 3], curves[c + 4], curves[c + 5],
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curves[c + 6], curves[c + 7], curves[c + 8],
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curves[c + 9], curves[c + 10], curves[c + 11],
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curves[c + 12], curves[c + 13]);
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}
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return 0;
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}
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/**
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* blank() - blank the display
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*
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* @par: FBTFT parameter object
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* @on: whether to enable or disable blanking the display
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*
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* Return: 0 on success, < 0 if error occurred.
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*/
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static int blank(struct fbtft_par *par, bool on)
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{
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if (on)
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write_reg(par, MIPI_DCS_SET_DISPLAY_OFF);
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else
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write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
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return 0;
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}
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static struct fbtft_display display = {
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.regwidth = 8,
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.width = 240,
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.height = 320,
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.gamma_num = 2,
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.gamma_len = 14,
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.gamma = HSD20_IPS_GAMMA,
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.fbtftops = {
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.init_display = init_display,
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.write_vmem = write_vmem,
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.set_var = set_var,
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.set_gamma = set_gamma,
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.blank = blank,
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},
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};
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FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7789v", &display);
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MODULE_ALIAS("spi:" DRVNAME);
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MODULE_ALIAS("platform:" DRVNAME);
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MODULE_ALIAS("spi:st7789v");
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MODULE_ALIAS("platform:st7789v");
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MODULE_DESCRIPTION("FB driver for the ST7789V LCD Controller");
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MODULE_AUTHOR("Dennis Menschel");
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MODULE_LICENSE("GPL");
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