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![Nicolas Pitre](/assets/img/avatar_default.png)
From PXA27x, it is possible to do 2048-byte block transfers. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
610 lines
14 KiB
C
610 lines
14 KiB
C
/*
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* linux/drivers/mmc/host/pxa.c - PXA MMCI driver
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*
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* Copyright (C) 2003 Russell King, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This hardware is really sick:
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* - No way to clear interrupts.
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* - Have to turn off the clock whenever we touch the device.
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* - Doesn't tell you how many data blocks were transferred.
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* Yuck!
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*
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* 1 and 3 byte data transfers not supported
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* max block length up to 1023
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/mmc/host.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/scatterlist.h>
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#include <asm/sizes.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/mmc.h>
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#include "pxamci.h"
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#define DRIVER_NAME "pxa2xx-mci"
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#define NR_SG 1
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struct pxamci_host {
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struct mmc_host *mmc;
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spinlock_t lock;
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struct resource *res;
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void __iomem *base;
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int irq;
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int dma;
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unsigned int clkrt;
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unsigned int cmdat;
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unsigned int imask;
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unsigned int power_mode;
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struct pxamci_platform_data *pdata;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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dma_addr_t sg_dma;
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struct pxa_dma_desc *sg_cpu;
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unsigned int dma_len;
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unsigned int dma_dir;
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};
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static void pxamci_stop_clock(struct pxamci_host *host)
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{
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if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
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unsigned long timeout = 10000;
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unsigned int v;
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writel(STOP_CLOCK, host->base + MMC_STRPCL);
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do {
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v = readl(host->base + MMC_STAT);
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if (!(v & STAT_CLK_EN))
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break;
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udelay(1);
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} while (timeout--);
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if (v & STAT_CLK_EN)
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dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
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}
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}
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static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->imask &= ~mask;
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writel(host->imask, host->base + MMC_I_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->imask |= mask;
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writel(host->imask, host->base + MMC_I_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
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{
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unsigned int nob = data->blocks;
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unsigned long long clks;
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unsigned int timeout;
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u32 dcmd;
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int i;
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host->data = data;
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if (data->flags & MMC_DATA_STREAM)
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nob = 0xffff;
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writel(nob, host->base + MMC_NOB);
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writel(data->blksz, host->base + MMC_BLKLEN);
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clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
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do_div(clks, 1000000000UL);
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timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
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writel((timeout + 255) / 256, host->base + MMC_RDTO);
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if (data->flags & MMC_DATA_READ) {
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host->dma_dir = DMA_FROM_DEVICE;
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dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
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DRCMRTXMMC = 0;
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DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
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} else {
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host->dma_dir = DMA_TO_DEVICE;
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dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
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DRCMRRXMMC = 0;
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DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
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}
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dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
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host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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host->dma_dir);
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for (i = 0; i < host->dma_len; i++) {
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if (data->flags & MMC_DATA_READ) {
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host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
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host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
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} else {
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host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
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host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
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}
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host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
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host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
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sizeof(struct pxa_dma_desc);
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}
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host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
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wmb();
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DDADR(host->dma) = host->sg_dma;
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DCSR(host->dma) = DCSR_RUN;
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}
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static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
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{
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WARN_ON(host->cmd != NULL);
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host->cmd = cmd;
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if (cmd->flags & MMC_RSP_BUSY)
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cmdat |= CMDAT_BUSY;
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#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
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switch (RSP_TYPE(mmc_resp_type(cmd))) {
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case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
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cmdat |= CMDAT_RESP_SHORT;
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break;
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case RSP_TYPE(MMC_RSP_R3):
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cmdat |= CMDAT_RESP_R3;
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break;
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case RSP_TYPE(MMC_RSP_R2):
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cmdat |= CMDAT_RESP_R2;
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break;
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default:
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break;
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}
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writel(cmd->opcode, host->base + MMC_CMD);
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writel(cmd->arg >> 16, host->base + MMC_ARGH);
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writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
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writel(cmdat, host->base + MMC_CMDAT);
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writel(host->clkrt, host->base + MMC_CLKRT);
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writel(START_CLOCK, host->base + MMC_STRPCL);
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pxamci_enable_irq(host, END_CMD_RES);
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}
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static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
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{
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host->mrq = NULL;
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host->cmd = NULL;
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host->data = NULL;
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mmc_request_done(host->mmc, mrq);
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}
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static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
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{
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struct mmc_command *cmd = host->cmd;
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int i;
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u32 v;
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if (!cmd)
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return 0;
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host->cmd = NULL;
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/*
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* Did I mention this is Sick. We always need to
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* discard the upper 8 bits of the first 16-bit word.
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*/
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v = readl(host->base + MMC_RES) & 0xffff;
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for (i = 0; i < 4; i++) {
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u32 w1 = readl(host->base + MMC_RES) & 0xffff;
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u32 w2 = readl(host->base + MMC_RES) & 0xffff;
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cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
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v = w2;
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}
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if (stat & STAT_TIME_OUT_RESPONSE) {
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cmd->error = -ETIMEDOUT;
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} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
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#ifdef CONFIG_PXA27x
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/*
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* workaround for erratum #42:
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* Intel PXA27x Family Processor Specification Update Rev 001
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* A bogus CRC error can appear if the msb of a 136 bit
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* response is a one.
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*/
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if (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000) {
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pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
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} else
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#endif
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cmd->error = -EILSEQ;
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}
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pxamci_disable_irq(host, END_CMD_RES);
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if (host->data && !cmd->error) {
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pxamci_enable_irq(host, DATA_TRAN_DONE);
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} else {
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pxamci_finish_request(host, host->mrq);
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}
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return 1;
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}
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static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
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{
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struct mmc_data *data = host->data;
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if (!data)
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return 0;
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DCSR(host->dma) = 0;
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
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host->dma_dir);
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if (stat & STAT_READ_TIME_OUT)
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data->error = -ETIMEDOUT;
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else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
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data->error = -EILSEQ;
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/*
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* There appears to be a hardware design bug here. There seems to
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* be no way to find out how much data was transferred to the card.
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* This means that if there was an error on any block, we mark all
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* data blocks as being in error.
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*/
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if (!data->error)
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data->bytes_xfered = data->blocks * data->blksz;
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else
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data->bytes_xfered = 0;
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pxamci_disable_irq(host, DATA_TRAN_DONE);
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host->data = NULL;
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if (host->mrq->stop) {
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pxamci_stop_clock(host);
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pxamci_start_cmd(host, host->mrq->stop, 0);
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} else {
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pxamci_finish_request(host, host->mrq);
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}
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return 1;
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}
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static irqreturn_t pxamci_irq(int irq, void *devid)
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{
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struct pxamci_host *host = devid;
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unsigned int ireg;
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int handled = 0;
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ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
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if (ireg) {
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unsigned stat = readl(host->base + MMC_STAT);
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pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
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if (ireg & END_CMD_RES)
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handled |= pxamci_cmd_done(host, stat);
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if (ireg & DATA_TRAN_DONE)
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handled |= pxamci_data_done(host, stat);
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}
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return IRQ_RETVAL(handled);
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}
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static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct pxamci_host *host = mmc_priv(mmc);
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unsigned int cmdat;
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WARN_ON(host->mrq != NULL);
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host->mrq = mrq;
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pxamci_stop_clock(host);
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cmdat = host->cmdat;
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host->cmdat &= ~CMDAT_INIT;
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if (mrq->data) {
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pxamci_setup_data(host, mrq->data);
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cmdat &= ~CMDAT_BUSY;
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cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
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if (mrq->data->flags & MMC_DATA_WRITE)
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cmdat |= CMDAT_WRITE;
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if (mrq->data->flags & MMC_DATA_STREAM)
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cmdat |= CMDAT_STREAM;
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}
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pxamci_start_cmd(host, mrq->cmd, cmdat);
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}
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static int pxamci_get_ro(struct mmc_host *mmc)
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{
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struct pxamci_host *host = mmc_priv(mmc);
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if (host->pdata && host->pdata->get_ro)
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return host->pdata->get_ro(mmc_dev(mmc));
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/* Host doesn't support read only detection so assume writeable */
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return 0;
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}
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static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct pxamci_host *host = mmc_priv(mmc);
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if (ios->clock) {
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unsigned int clk = CLOCKRATE / ios->clock;
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if (CLOCKRATE / clk > ios->clock)
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clk <<= 1;
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host->clkrt = fls(clk) - 1;
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pxa_set_cken(CKEN_MMC, 1);
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/*
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* we write clkrt on the next command
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*/
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} else {
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pxamci_stop_clock(host);
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pxa_set_cken(CKEN_MMC, 0);
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}
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if (host->power_mode != ios->power_mode) {
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host->power_mode = ios->power_mode;
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if (host->pdata && host->pdata->setpower)
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host->pdata->setpower(mmc_dev(mmc), ios->vdd);
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if (ios->power_mode == MMC_POWER_ON)
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host->cmdat |= CMDAT_INIT;
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}
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pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
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host->clkrt, host->cmdat);
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}
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static const struct mmc_host_ops pxamci_ops = {
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.request = pxamci_request,
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.get_ro = pxamci_get_ro,
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.set_ios = pxamci_set_ios,
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};
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static void pxamci_dma_irq(int dma, void *devid)
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{
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printk(KERN_ERR "DMA%d: IRQ???\n", dma);
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DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
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}
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static irqreturn_t pxamci_detect_irq(int irq, void *devid)
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{
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struct pxamci_host *host = mmc_priv(devid);
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mmc_detect_change(devid, host->pdata->detect_delay);
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return IRQ_HANDLED;
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}
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static int pxamci_probe(struct platform_device *pdev)
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{
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struct mmc_host *mmc;
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struct pxamci_host *host = NULL;
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struct resource *r;
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int ret, irq;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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irq = platform_get_irq(pdev, 0);
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if (!r || irq < 0)
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return -ENXIO;
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r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
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if (!r)
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return -EBUSY;
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mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
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if (!mmc) {
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ret = -ENOMEM;
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goto out;
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}
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mmc->ops = &pxamci_ops;
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mmc->f_min = CLOCKRATE_MIN;
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mmc->f_max = CLOCKRATE_MAX;
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/*
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* We can do SG-DMA, but we don't because we never know how much
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* data we successfully wrote to the card.
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*/
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mmc->max_phys_segs = NR_SG;
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/*
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* Our hardware DMA can handle a maximum of one page per SG entry.
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*/
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mmc->max_seg_size = PAGE_SIZE;
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/*
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* Block length register is only 10 bits before PXA27x.
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*/
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mmc->max_blk_size = (cpu_is_pxa21x() || cpu_is_pxa25x()) ? 1023 : 2048;
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/*
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* Block count register is 16 bits.
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*/
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mmc->max_blk_count = 65535;
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host = mmc_priv(mmc);
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host->mmc = mmc;
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host->dma = -1;
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host->pdata = pdev->dev.platform_data;
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mmc->ocr_avail = host->pdata ?
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host->pdata->ocr_mask :
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MMC_VDD_32_33|MMC_VDD_33_34;
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host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
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if (!host->sg_cpu) {
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ret = -ENOMEM;
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goto out;
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}
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spin_lock_init(&host->lock);
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host->res = r;
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host->irq = irq;
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host->imask = MMC_I_MASK_ALL;
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host->base = ioremap(r->start, SZ_4K);
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if (!host->base) {
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ret = -ENOMEM;
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goto out;
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}
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/*
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* Ensure that the host controller is shut down, and setup
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* with our defaults.
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*/
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pxamci_stop_clock(host);
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writel(0, host->base + MMC_SPI);
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writel(64, host->base + MMC_RESTO);
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writel(host->imask, host->base + MMC_I_MASK);
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host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
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pxamci_dma_irq, host);
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if (host->dma < 0) {
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ret = -EBUSY;
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goto out;
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}
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ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
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if (ret)
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goto out;
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platform_set_drvdata(pdev, mmc);
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|
|
if (host->pdata && host->pdata->init)
|
|
host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
return 0;
|
|
|
|
out:
|
|
if (host) {
|
|
if (host->dma >= 0)
|
|
pxa_free_dma(host->dma);
|
|
if (host->base)
|
|
iounmap(host->base);
|
|
if (host->sg_cpu)
|
|
dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
|
|
}
|
|
if (mmc)
|
|
mmc_free_host(mmc);
|
|
release_resource(r);
|
|
return ret;
|
|
}
|
|
|
|
static int pxamci_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
if (mmc) {
|
|
struct pxamci_host *host = mmc_priv(mmc);
|
|
|
|
if (host->pdata && host->pdata->exit)
|
|
host->pdata->exit(&pdev->dev, mmc);
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
pxamci_stop_clock(host);
|
|
writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
|
|
END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
|
|
host->base + MMC_I_MASK);
|
|
|
|
DRCMRRXMMC = 0;
|
|
DRCMRTXMMC = 0;
|
|
|
|
free_irq(host->irq, host);
|
|
pxa_free_dma(host->dma);
|
|
iounmap(host->base);
|
|
dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
|
|
|
|
release_resource(host->res);
|
|
|
|
mmc_free_host(mmc);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
if (mmc)
|
|
ret = mmc_suspend_host(mmc, state);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int pxamci_resume(struct platform_device *dev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
if (mmc)
|
|
ret = mmc_resume_host(mmc);
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
#define pxamci_suspend NULL
|
|
#define pxamci_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver pxamci_driver = {
|
|
.probe = pxamci_probe,
|
|
.remove = pxamci_remove,
|
|
.suspend = pxamci_suspend,
|
|
.resume = pxamci_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
static int __init pxamci_init(void)
|
|
{
|
|
return platform_driver_register(&pxamci_driver);
|
|
}
|
|
|
|
static void __exit pxamci_exit(void)
|
|
{
|
|
platform_driver_unregister(&pxamci_driver);
|
|
}
|
|
|
|
module_init(pxamci_init);
|
|
module_exit(pxamci_exit);
|
|
|
|
MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
|
|
MODULE_LICENSE("GPL");
|