Andy Shevchenko fe364a7d95 dmaengine: dw: Program xBAR hardware for Elkhart Lake ... Intel Elkhart Lake PSE DMA implementation is integrated with crossbar IP in order to serve more hardware than there are DMA request lines available. Due to this, program xBAR hardware to make flexible support of PSE peripheral. The Device-to-Device has not been tested and it's not supported by DMA Engine, but it's left in the code for the sake of documenting hardware features. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210712113940.42753-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2021-07-14 10:16:30 +05:30
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acpi.c	dmaengine: dw: Register ACPI DMA controller for PCI that has companion	2020-06-16 21:54:47 +05:30
core.c	dmaengine dw: Revert "dmaengine: dw: Enable runtime PM"	2021-02-08 17:36:12 +05:30
dw.c	dmaengine: dw: Ignore burst setting for memory peripherals	2020-08-17 11:58:31 +05:30
idma32.c	dmaengine: dw: Program xBAR hardware for Elkhart Lake	2021-07-14 10:16:30 +05:30
internal.h	dmaengine: dw: Program xBAR hardware for Elkhart Lake	2021-07-14 10:16:30 +05:30
Kconfig	dmaengine: dw: Make it dependent to HAS_IOMEM	2021-04-12 14:54:45 +05:30
Makefile	dmaengine: dw: Replace 'objs' by 'y'	2020-06-16 21:54:47 +05:30
of.c	dmaengine: dw: Add DMA-channels mask cell support	2020-08-17 11:58:31 +05:30
pci.c	dmaengine: dw: Program xBAR hardware for Elkhart Lake	2021-07-14 10:16:30 +05:30
platform.c	dmaengine: dw: Program xBAR hardware for Elkhart Lake	2021-07-14 10:16:30 +05:30
regs.h	dmaengine: dw: Introduce max burst length hw config	2020-07-27 14:30:55 +05:30