Vineet Gupta fe6c1b8611 ARCv2: mm: THP support ... MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP support. Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a new bit "SZ" in TLB page desciptor to distinguish between them. Super Page size is configurable in hardware (4K to 16M), but fixed once RTL builds. The exact THP size a Linx configuration will support is a function of: - MMU page size (typical 8K, RTL fixed) - software page walker address split between PGD:PTE:PFN (typical 11:8:13, but can be changed with 1 line) So for above default, THP size supported is 8K * 256 = 2M Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime reduces to 1 level (as PTE is folded into PGD and canonically referred to as PMD). Thus thp PMD accessors are implemented in terms of PTE (just like sparc) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-10-17 17:48:18 +05:30
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cache.c	ARC: Eliminate some ARCv2 specific code for ARCompact build	2015-08-21 15:06:43 +05:30
dma.c	ARC: Eliminate some ARCv2 specific code for ARCompact build	2015-08-21 15:06:43 +05:30
extable.c	ARC: Fix coding style issues	2013-04-09 12:21:14 +05:30
fault.c	mm/fault, arch: Use pagefault_disable() to check for disabled pagefaults in the handler	2015-05-19 08:39:15 +02:00
init.c	ARC: mem init spring cleaning - No functional changes	2015-04-13 15:16:29 +05:30
ioremap.c	ARC: Use <linux/*> headers instead of <asm/*>	2013-04-09 12:21:14 +05:30
Makefile	ARC: mm/cache_arc700.c -> mm/cache.c	2015-06-19 18:09:32 +05:30
mmap.c	ARC: [mm] Aliasing VIPT dcache support 4/4	2013-05-09 22:00:57 +05:30
tlb.c	ARCv2: mm: THP support	2015-10-17 17:48:18 +05:30
tlbex.S	ARCv2: mm: THP support	2015-10-17 17:48:18 +05:30