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![Alex Deucher](/assets/img/avatar_default.png)
Don't init fbdev if we don't have connectors. E.g., if you have a PX laptop with the displays attached to an IGP with no driver support, you may end up with a blank screen rather than falling back to vesa, etc. Based on a similar radeon patch from Rob Clark. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
424 lines
11 KiB
C
424 lines
11 KiB
C
/*
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* Copyright © 2007 David Airlie
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* David Airlie
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*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/fb.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "cikd.h"
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#include <drm/drm_fb_helper.h>
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#include <linux/vga_switcheroo.h>
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/* object hierarchy -
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this contains a helper + a amdgpu fb
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the helper contains a pointer to amdgpu framebuffer baseclass.
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*/
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struct amdgpu_fbdev {
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struct drm_fb_helper helper;
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struct amdgpu_framebuffer rfb;
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struct amdgpu_device *adev;
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};
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static struct fb_ops amdgpufb_ops = {
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.owner = THIS_MODULE,
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.fb_check_var = drm_fb_helper_check_var,
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.fb_set_par = drm_fb_helper_set_par,
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.fb_fillrect = drm_fb_helper_cfb_fillrect,
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.fb_copyarea = drm_fb_helper_cfb_copyarea,
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.fb_imageblit = drm_fb_helper_cfb_imageblit,
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.fb_pan_display = drm_fb_helper_pan_display,
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.fb_blank = drm_fb_helper_blank,
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.fb_setcmap = drm_fb_helper_setcmap,
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.fb_debug_enter = drm_fb_helper_debug_enter,
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.fb_debug_leave = drm_fb_helper_debug_leave,
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};
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int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled)
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{
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int aligned = width;
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int pitch_mask = 0;
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switch (bpp / 8) {
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case 1:
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pitch_mask = 255;
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break;
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case 2:
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pitch_mask = 127;
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break;
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case 3:
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case 4:
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pitch_mask = 63;
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break;
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}
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aligned += pitch_mask;
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aligned &= ~pitch_mask;
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return aligned;
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}
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static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
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{
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struct amdgpu_bo *rbo = gem_to_amdgpu_bo(gobj);
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int ret;
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ret = amdgpu_bo_reserve(rbo, false);
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if (likely(ret == 0)) {
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amdgpu_bo_kunmap(rbo);
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amdgpu_bo_unpin(rbo);
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amdgpu_bo_unreserve(rbo);
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}
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drm_gem_object_unreference_unlocked(gobj);
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}
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static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
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struct drm_mode_fb_cmd2 *mode_cmd,
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struct drm_gem_object **gobj_p)
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{
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struct amdgpu_device *adev = rfbdev->adev;
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struct drm_gem_object *gobj = NULL;
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struct amdgpu_bo *rbo = NULL;
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bool fb_tiled = false; /* useful for testing */
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u32 tiling_flags = 0;
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int ret;
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int aligned_size, size;
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int height = mode_cmd->height;
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u32 bpp, depth;
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drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
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/* need to align pitch with crtc limits */
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mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, bpp,
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fb_tiled) * ((bpp + 1) / 8);
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height = ALIGN(mode_cmd->height, 8);
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size = mode_cmd->pitches[0] * height;
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aligned_size = ALIGN(size, PAGE_SIZE);
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ret = amdgpu_gem_object_create(adev, aligned_size, 0,
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AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
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true, &gobj);
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if (ret) {
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printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
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aligned_size);
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return -ENOMEM;
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}
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rbo = gem_to_amdgpu_bo(gobj);
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if (fb_tiled)
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tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
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ret = amdgpu_bo_reserve(rbo, false);
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if (unlikely(ret != 0))
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goto out_unref;
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if (tiling_flags) {
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ret = amdgpu_bo_set_tiling_flags(rbo,
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tiling_flags);
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if (ret)
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dev_err(adev->dev, "FB failed to set tiling flags\n");
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}
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ret = amdgpu_bo_pin_restricted(rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL);
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if (ret) {
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amdgpu_bo_unreserve(rbo);
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goto out_unref;
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}
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ret = amdgpu_bo_kmap(rbo, NULL);
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amdgpu_bo_unreserve(rbo);
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if (ret) {
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goto out_unref;
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}
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*gobj_p = gobj;
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return 0;
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out_unref:
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amdgpufb_destroy_pinned_object(gobj);
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*gobj_p = NULL;
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return ret;
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}
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static int amdgpufb_create(struct drm_fb_helper *helper,
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struct drm_fb_helper_surface_size *sizes)
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{
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struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
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struct amdgpu_device *adev = rfbdev->adev;
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struct fb_info *info;
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struct drm_framebuffer *fb = NULL;
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struct drm_mode_fb_cmd2 mode_cmd;
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struct drm_gem_object *gobj = NULL;
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struct amdgpu_bo *rbo = NULL;
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int ret;
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unsigned long tmp;
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mode_cmd.width = sizes->surface_width;
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mode_cmd.height = sizes->surface_height;
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if (sizes->surface_bpp == 24)
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sizes->surface_bpp = 32;
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mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
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sizes->surface_depth);
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ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
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if (ret) {
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DRM_ERROR("failed to create fbcon object %d\n", ret);
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return ret;
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}
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rbo = gem_to_amdgpu_bo(gobj);
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/* okay we have an object now allocate the framebuffer */
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info = drm_fb_helper_alloc_fbi(helper);
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if (IS_ERR(info)) {
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ret = PTR_ERR(info);
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goto out_unref;
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}
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info->par = rfbdev;
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info->skip_vt_switch = true;
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ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
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if (ret) {
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DRM_ERROR("failed to initialize framebuffer %d\n", ret);
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goto out_destroy_fbi;
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}
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fb = &rfbdev->rfb.base;
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/* setup helper */
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rfbdev->helper.fb = fb;
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memset_io(rbo->kptr, 0x0, amdgpu_bo_size(rbo));
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strcpy(info->fix.id, "amdgpudrmfb");
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drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
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info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
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info->fbops = &amdgpufb_ops;
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tmp = amdgpu_bo_gpu_offset(rbo) - adev->mc.vram_start;
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info->fix.smem_start = adev->mc.aper_base + tmp;
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info->fix.smem_len = amdgpu_bo_size(rbo);
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info->screen_base = rbo->kptr;
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info->screen_size = amdgpu_bo_size(rbo);
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drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
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/* setup aperture base/size for vesafb takeover */
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info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
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info->apertures->ranges[0].size = adev->mc.aper_size;
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/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
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if (info->screen_base == NULL) {
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ret = -ENOSPC;
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goto out_destroy_fbi;
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}
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DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
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DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base);
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DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(rbo));
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DRM_INFO("fb depth is %d\n", fb->depth);
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DRM_INFO(" pitch is %d\n", fb->pitches[0]);
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vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
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return 0;
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out_destroy_fbi:
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drm_fb_helper_release_fbi(helper);
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out_unref:
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if (rbo) {
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}
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if (fb && ret) {
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drm_gem_object_unreference_unlocked(gobj);
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drm_framebuffer_unregister_private(fb);
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drm_framebuffer_cleanup(fb);
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kfree(fb);
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}
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return ret;
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}
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void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
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{
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if (adev->mode_info.rfbdev)
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drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
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}
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static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
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{
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struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
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drm_fb_helper_unregister_fbi(&rfbdev->helper);
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drm_fb_helper_release_fbi(&rfbdev->helper);
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if (rfb->obj) {
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amdgpufb_destroy_pinned_object(rfb->obj);
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rfb->obj = NULL;
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}
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drm_fb_helper_fini(&rfbdev->helper);
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drm_framebuffer_unregister_private(&rfb->base);
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drm_framebuffer_cleanup(&rfb->base);
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return 0;
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}
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/** Sets the color ramps on behalf of fbcon */
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static void amdgpu_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
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u16 blue, int regno)
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{
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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amdgpu_crtc->lut_r[regno] = red >> 6;
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amdgpu_crtc->lut_g[regno] = green >> 6;
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amdgpu_crtc->lut_b[regno] = blue >> 6;
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}
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/** Gets the color ramps on behalf of fbcon */
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static void amdgpu_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
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u16 *blue, int regno)
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{
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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*red = amdgpu_crtc->lut_r[regno] << 6;
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*green = amdgpu_crtc->lut_g[regno] << 6;
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*blue = amdgpu_crtc->lut_b[regno] << 6;
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}
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static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
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.gamma_set = amdgpu_crtc_fb_gamma_set,
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.gamma_get = amdgpu_crtc_fb_gamma_get,
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.fb_probe = amdgpufb_create,
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};
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int amdgpu_fbdev_init(struct amdgpu_device *adev)
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{
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struct amdgpu_fbdev *rfbdev;
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int bpp_sel = 32;
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int ret;
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/* don't init fbdev on hw without DCE */
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if (!adev->mode_info.mode_config_initialized)
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return 0;
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/* don't init fbdev if there are no connectors */
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if (list_empty(&adev->ddev->mode_config.connector_list))
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return 0;
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/* select 8 bpp console on low vram cards */
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if (adev->mc.real_vram_size <= (32*1024*1024))
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bpp_sel = 8;
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rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
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if (!rfbdev)
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return -ENOMEM;
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rfbdev->adev = adev;
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adev->mode_info.rfbdev = rfbdev;
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drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
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&amdgpu_fb_helper_funcs);
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ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
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adev->mode_info.num_crtc,
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AMDGPUFB_CONN_LIMIT);
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if (ret) {
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kfree(rfbdev);
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return ret;
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}
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drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
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/* disable all the possible outputs/crtcs before entering KMS mode */
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drm_helper_disable_unused_functions(adev->ddev);
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drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
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return 0;
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}
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void amdgpu_fbdev_fini(struct amdgpu_device *adev)
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{
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if (!adev->mode_info.rfbdev)
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return;
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amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
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kfree(adev->mode_info.rfbdev);
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adev->mode_info.rfbdev = NULL;
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}
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void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
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{
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if (adev->mode_info.rfbdev)
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drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
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state);
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}
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int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
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{
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struct amdgpu_bo *robj;
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int size = 0;
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if (!adev->mode_info.rfbdev)
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return 0;
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robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
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size += amdgpu_bo_size(robj);
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return size;
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}
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bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
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{
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if (!adev->mode_info.rfbdev)
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return false;
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if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
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return true;
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return false;
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}
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void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
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{
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struct amdgpu_fbdev *afbdev = adev->mode_info.rfbdev;
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struct drm_fb_helper *fb_helper;
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int ret;
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if (!afbdev)
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return;
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fb_helper = &afbdev->helper;
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ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
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if (ret)
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DRM_DEBUG("failed to restore crtc mode\n");
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}
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