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![Christian König](/assets/img/avatar_default.png)
Try to avoid using the hardware specific fences even more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
753 lines
21 KiB
C
753 lines
21 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Dave Airlie
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*/
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#include <linux/seq_file.h>
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#include <linux/atomic.h>
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#include <linux/wait.h>
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#include <linux/kref.h>
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#include <linux/slab.h>
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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/*
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* Fences
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* Fences mark an event in the GPUs pipeline and are used
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* for GPU/CPU synchronization. When the fence is written,
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* it is expected that all buffers associated with that fence
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* are no longer in use by the associated ring on the GPU and
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* that the the relevant GPU caches have been flushed.
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*/
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static struct kmem_cache *amdgpu_fence_slab;
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static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0);
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/**
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* amdgpu_fence_write - write a fence value
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*
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* @ring: ring the fence is associated with
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* @seq: sequence number to write
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*
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* Writes a fence value to memory (all asics).
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*/
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static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
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{
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struct amdgpu_fence_driver *drv = &ring->fence_drv;
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if (drv->cpu_addr)
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*drv->cpu_addr = cpu_to_le32(seq);
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}
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/**
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* amdgpu_fence_read - read a fence value
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*
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* @ring: ring the fence is associated with
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*
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* Reads a fence value from memory (all asics).
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* Returns the value of the fence read from memory.
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*/
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static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
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{
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struct amdgpu_fence_driver *drv = &ring->fence_drv;
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u32 seq = 0;
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if (drv->cpu_addr)
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seq = le32_to_cpu(*drv->cpu_addr);
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else
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seq = lower_32_bits(atomic64_read(&drv->last_seq));
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return seq;
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}
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/**
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* amdgpu_fence_emit - emit a fence on the requested ring
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*
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* @ring: ring the fence is associated with
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* @f: resulting fence object
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*
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* Emits a fence command on the requested ring (all asics).
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* Returns 0 on success, -ENOMEM on failure.
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*/
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int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_fence *fence;
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fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
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if (fence == NULL)
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return -ENOMEM;
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fence->seq = ++ring->fence_drv.sync_seq;
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fence->ring = ring;
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fence_init(&fence->base, &amdgpu_fence_ops,
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&ring->fence_drv.fence_queue.lock,
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adev->fence_context + ring->idx,
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fence->seq);
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amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
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fence->seq, AMDGPU_FENCE_FLAG_INT);
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*f = &fence->base;
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return 0;
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}
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/**
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* amdgpu_fence_schedule_fallback - schedule fallback check
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*
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* @ring: pointer to struct amdgpu_ring
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*
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* Start a timer as fallback to our interrupts.
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*/
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static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
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{
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mod_timer(&ring->fence_drv.fallback_timer,
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jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
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}
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/**
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* amdgpu_fence_activity - check for fence activity
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*
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* @ring: pointer to struct amdgpu_ring
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*
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* Checks the current fence value and calculates the last
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* signalled fence value. Returns true if activity occured
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* on the ring, and the fence_queue should be waken up.
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*/
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static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
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{
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uint64_t seq, last_seq, last_emitted;
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unsigned count_loop = 0;
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bool wake = false;
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/* Note there is a scenario here for an infinite loop but it's
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* very unlikely to happen. For it to happen, the current polling
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* process need to be interrupted by another process and another
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* process needs to update the last_seq btw the atomic read and
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* xchg of the current process.
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*
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* More over for this to go in infinite loop there need to be
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* continuously new fence signaled ie amdgpu_fence_read needs
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* to return a different value each time for both the currently
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* polling process and the other process that xchg the last_seq
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* btw atomic read and xchg of the current process. And the
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* value the other process set as last seq must be higher than
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* the seq value we just read. Which means that current process
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* need to be interrupted after amdgpu_fence_read and before
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* atomic xchg.
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*
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* To be even more safe we count the number of time we loop and
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* we bail after 10 loop just accepting the fact that we might
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* have temporarly set the last_seq not to the true real last
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* seq but to an older one.
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*/
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last_seq = atomic64_read(&ring->fence_drv.last_seq);
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do {
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last_emitted = ring->fence_drv.sync_seq;
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seq = amdgpu_fence_read(ring);
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seq |= last_seq & 0xffffffff00000000LL;
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if (seq < last_seq) {
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seq &= 0xffffffff;
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seq |= last_emitted & 0xffffffff00000000LL;
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}
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if (seq <= last_seq || seq > last_emitted) {
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break;
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}
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/* If we loop over we don't want to return without
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* checking if a fence is signaled as it means that the
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* seq we just read is different from the previous on.
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*/
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wake = true;
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last_seq = seq;
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if ((count_loop++) > 10) {
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/* We looped over too many time leave with the
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* fact that we might have set an older fence
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* seq then the current real last seq as signaled
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* by the hw.
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*/
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break;
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}
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} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
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if (seq < last_emitted)
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amdgpu_fence_schedule_fallback(ring);
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return wake;
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}
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/**
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* amdgpu_fence_process - process a fence
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*
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* @adev: amdgpu_device pointer
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* @ring: ring index the fence is associated with
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*
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* Checks the current fence value and wakes the fence queue
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* if the sequence number has increased (all asics).
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*/
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void amdgpu_fence_process(struct amdgpu_ring *ring)
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{
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if (amdgpu_fence_activity(ring))
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wake_up_all(&ring->fence_drv.fence_queue);
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}
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/**
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* amdgpu_fence_fallback - fallback for hardware interrupts
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*
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* @work: delayed work item
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*
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* Checks for fence activity.
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*/
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static void amdgpu_fence_fallback(unsigned long arg)
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{
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struct amdgpu_ring *ring = (void *)arg;
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amdgpu_fence_process(ring);
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}
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/**
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* amdgpu_fence_seq_signaled - check if a fence sequence number has signaled
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*
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* @ring: ring the fence is associated with
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* @seq: sequence number
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*
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* Check if the last signaled fence sequnce number is >= the requested
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* sequence number (all asics).
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* Returns true if the fence has signaled (current fence value
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* is >= requested value) or false if it has not (current fence
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* value is < the requested value. Helper function for
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* amdgpu_fence_signaled().
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*/
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static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
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{
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if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
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return true;
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/* poll new last sequence at least once */
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amdgpu_fence_process(ring);
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if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
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return true;
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return false;
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}
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/*
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* amdgpu_ring_wait_seq - wait for seq of the specific ring to signal
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* @ring: ring to wait on for the seq number
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* @seq: seq number wait for
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*
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* return value:
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* 0: seq signaled, and gpu not hang
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* -EINVAL: some paramter is not valid
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*/
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static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
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{
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BUG_ON(!ring);
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if (seq > ring->fence_drv.sync_seq)
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return -EINVAL;
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if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
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return 0;
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amdgpu_fence_schedule_fallback(ring);
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wait_event(ring->fence_drv.fence_queue,
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amdgpu_fence_seq_signaled(ring, seq));
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return 0;
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}
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/**
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* amdgpu_fence_wait_next - wait for the next fence to signal
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*
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* @adev: amdgpu device pointer
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* @ring: ring index the fence is associated with
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*
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* Wait for the next fence on the requested ring to signal (all asics).
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* Returns 0 if the next fence has passed, error for all other cases.
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* Caller must hold ring lock.
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*/
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int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
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{
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uint64_t seq = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
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if (seq >= ring->fence_drv.sync_seq)
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return -ENOENT;
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return amdgpu_fence_ring_wait_seq(ring, seq);
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}
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/**
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* amdgpu_fence_wait_empty - wait for all fences to signal
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*
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* @adev: amdgpu device pointer
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* @ring: ring index the fence is associated with
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*
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* Wait for all fences on the requested ring to signal (all asics).
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* Returns 0 if the fences have passed, error for all other cases.
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* Caller must hold ring lock.
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*/
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
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{
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uint64_t seq = ring->fence_drv.sync_seq;
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if (!seq)
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return 0;
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return amdgpu_fence_ring_wait_seq(ring, seq);
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}
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/**
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* amdgpu_fence_count_emitted - get the count of emitted fences
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*
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* @ring: ring the fence is associated with
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*
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* Get the number of fences emitted on the requested ring (all asics).
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* Returns the number of emitted fences on the ring. Used by the
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* dynpm code to ring track activity.
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*/
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unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
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{
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uint64_t emitted;
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/* We are not protected by ring lock when reading the last sequence
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* but it's ok to report slightly wrong fence count here.
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*/
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amdgpu_fence_process(ring);
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emitted = ring->fence_drv.sync_seq
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- atomic64_read(&ring->fence_drv.last_seq);
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/* to avoid 32bits warp around */
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if (emitted > 0x10000000)
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emitted = 0x10000000;
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return (unsigned)emitted;
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}
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/**
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* amdgpu_fence_driver_start_ring - make the fence driver
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* ready for use on the requested ring.
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*
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* @ring: ring to start the fence driver on
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* @irq_src: interrupt source to use for this ring
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* @irq_type: interrupt type to use for this ring
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*
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* Make the fence driver ready for processing (all asics).
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* Not all asics have all rings, so each asic will only
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* start the fence driver on the rings it has.
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* Returns 0 for success, errors for failure.
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*/
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int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq_src,
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unsigned irq_type)
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{
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struct amdgpu_device *adev = ring->adev;
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uint64_t index;
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if (ring != &adev->uvd.ring) {
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ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
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ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
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} else {
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/* put fence directly behind firmware */
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index = ALIGN(adev->uvd.fw->size, 8);
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ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
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ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
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}
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amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
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amdgpu_irq_get(adev, irq_src, irq_type);
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ring->fence_drv.irq_src = irq_src;
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ring->fence_drv.irq_type = irq_type;
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ring->fence_drv.initialized = true;
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dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
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"cpu addr 0x%p\n", ring->idx,
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ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
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return 0;
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}
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/**
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* amdgpu_fence_driver_init_ring - init the fence driver
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* for the requested ring.
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*
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* @ring: ring to init the fence driver on
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*
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* Init the fence driver for the requested ring (all asics).
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* Helper function for amdgpu_fence_driver_init().
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*/
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
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{
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long timeout;
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int r;
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ring->fence_drv.cpu_addr = NULL;
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ring->fence_drv.gpu_addr = 0;
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ring->fence_drv.sync_seq = 0;
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atomic64_set(&ring->fence_drv.last_seq, 0);
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ring->fence_drv.initialized = false;
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setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
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(unsigned long)ring);
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init_waitqueue_head(&ring->fence_drv.fence_queue);
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timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
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if (timeout == 0) {
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/*
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* FIXME:
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* Delayed workqueue cannot use it directly,
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* so the scheduler will not use delayed workqueue if
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* MAX_SCHEDULE_TIMEOUT is set.
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* Currently keep it simple and silly.
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*/
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timeout = MAX_SCHEDULE_TIMEOUT;
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}
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r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
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amdgpu_sched_hw_submission,
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timeout, ring->name);
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if (r) {
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DRM_ERROR("Failed to create scheduler on ring %s.\n",
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ring->name);
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return r;
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}
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return 0;
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}
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/**
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* amdgpu_fence_driver_init - init the fence driver
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* for all possible rings.
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*
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* @adev: amdgpu device pointer
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*
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* Init the fence driver for all possible rings (all asics).
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* Not all asics have all rings, so each asic will only
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* start the fence driver on the rings it has using
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* amdgpu_fence_driver_start_ring().
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* Returns 0 for success.
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*/
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int amdgpu_fence_driver_init(struct amdgpu_device *adev)
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{
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if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) {
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amdgpu_fence_slab = kmem_cache_create(
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"amdgpu_fence", sizeof(struct amdgpu_fence), 0,
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SLAB_HWCACHE_ALIGN, NULL);
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if (!amdgpu_fence_slab)
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return -ENOMEM;
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}
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if (amdgpu_debugfs_fence_init(adev))
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dev_err(adev->dev, "fence debugfs file creation failed\n");
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return 0;
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}
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/**
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* amdgpu_fence_driver_fini - tear down the fence driver
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* for all possible rings.
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*
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* @adev: amdgpu device pointer
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*
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* Tear down the fence driver for all possible rings (all asics).
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*/
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void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
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{
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int i, r;
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if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
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kmem_cache_destroy(amdgpu_fence_slab);
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for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
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struct amdgpu_ring *ring = adev->rings[i];
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if (!ring || !ring->fence_drv.initialized)
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continue;
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r = amdgpu_fence_wait_empty(ring);
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if (r) {
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/* no need to trigger GPU reset as we are unloading */
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amdgpu_fence_driver_force_completion(adev);
|
|
}
|
|
wake_up_all(&ring->fence_drv.fence_queue);
|
|
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
|
|
ring->fence_drv.irq_type);
|
|
amd_sched_fini(&ring->sched);
|
|
del_timer_sync(&ring->fence_drv.fallback_timer);
|
|
ring->fence_drv.initialized = false;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* amdgpu_fence_driver_suspend - suspend the fence driver
|
|
* for all possible rings.
|
|
*
|
|
* @adev: amdgpu device pointer
|
|
*
|
|
* Suspend the fence driver for all possible rings (all asics).
|
|
*/
|
|
void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
|
|
{
|
|
int i, r;
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
if (!ring || !ring->fence_drv.initialized)
|
|
continue;
|
|
|
|
/* wait for gpu to finish processing current batch */
|
|
r = amdgpu_fence_wait_empty(ring);
|
|
if (r) {
|
|
/* delay GPU reset to resume */
|
|
amdgpu_fence_driver_force_completion(adev);
|
|
}
|
|
|
|
/* disable the interrupt */
|
|
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
|
|
ring->fence_drv.irq_type);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* amdgpu_fence_driver_resume - resume the fence driver
|
|
* for all possible rings.
|
|
*
|
|
* @adev: amdgpu device pointer
|
|
*
|
|
* Resume the fence driver for all possible rings (all asics).
|
|
* Not all asics have all rings, so each asic will only
|
|
* start the fence driver on the rings it has using
|
|
* amdgpu_fence_driver_start_ring().
|
|
* Returns 0 for success.
|
|
*/
|
|
void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
if (!ring || !ring->fence_drv.initialized)
|
|
continue;
|
|
|
|
/* enable the interrupt */
|
|
amdgpu_irq_get(adev, ring->fence_drv.irq_src,
|
|
ring->fence_drv.irq_type);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* amdgpu_fence_driver_force_completion - force all fence waiter to complete
|
|
*
|
|
* @adev: amdgpu device pointer
|
|
*
|
|
* In case of GPU reset failure make sure no process keep waiting on fence
|
|
* that will never complete.
|
|
*/
|
|
void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
if (!ring || !ring->fence_drv.initialized)
|
|
continue;
|
|
|
|
amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Common fence implementation
|
|
*/
|
|
|
|
static const char *amdgpu_fence_get_driver_name(struct fence *fence)
|
|
{
|
|
return "amdgpu";
|
|
}
|
|
|
|
static const char *amdgpu_fence_get_timeline_name(struct fence *f)
|
|
{
|
|
struct amdgpu_fence *fence = to_amdgpu_fence(f);
|
|
return (const char *)fence->ring->name;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_fence_is_signaled - test if fence is signaled
|
|
*
|
|
* @f: fence to test
|
|
*
|
|
* Test the fence sequence number if it is already signaled. If it isn't
|
|
* signaled start fence processing. Returns True if the fence is signaled.
|
|
*/
|
|
static bool amdgpu_fence_is_signaled(struct fence *f)
|
|
{
|
|
struct amdgpu_fence *fence = to_amdgpu_fence(f);
|
|
struct amdgpu_ring *ring = fence->ring;
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
|
|
return true;
|
|
|
|
amdgpu_fence_process(ring);
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_fence_check_signaled - callback from fence_queue
|
|
*
|
|
* this function is called with fence_queue lock held, which is also used
|
|
* for the fence locking itself, so unlocked variants are used for
|
|
* fence_signal, and remove_wait_queue.
|
|
*/
|
|
static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
|
|
{
|
|
struct amdgpu_fence *fence;
|
|
struct amdgpu_device *adev;
|
|
u64 seq;
|
|
int ret;
|
|
|
|
fence = container_of(wait, struct amdgpu_fence, fence_wake);
|
|
adev = fence->ring->adev;
|
|
|
|
/*
|
|
* We cannot use amdgpu_fence_process here because we're already
|
|
* in the waitqueue, in a call from wake_up_all.
|
|
*/
|
|
seq = atomic64_read(&fence->ring->fence_drv.last_seq);
|
|
if (seq >= fence->seq) {
|
|
ret = fence_signal_locked(&fence->base);
|
|
if (!ret)
|
|
FENCE_TRACE(&fence->base, "signaled from irq context\n");
|
|
else
|
|
FENCE_TRACE(&fence->base, "was already signaled\n");
|
|
|
|
__remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake);
|
|
fence_put(&fence->base);
|
|
} else
|
|
FENCE_TRACE(&fence->base, "pending\n");
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_fence_enable_signaling - enable signalling on fence
|
|
* @fence: fence
|
|
*
|
|
* This function is called with fence_queue lock held, and adds a callback
|
|
* to fence_queue that checks if this fence is signaled, and if so it
|
|
* signals the fence and removes itself.
|
|
*/
|
|
static bool amdgpu_fence_enable_signaling(struct fence *f)
|
|
{
|
|
struct amdgpu_fence *fence = to_amdgpu_fence(f);
|
|
struct amdgpu_ring *ring = fence->ring;
|
|
|
|
if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
|
|
return false;
|
|
|
|
fence->fence_wake.flags = 0;
|
|
fence->fence_wake.private = NULL;
|
|
fence->fence_wake.func = amdgpu_fence_check_signaled;
|
|
__add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake);
|
|
fence_get(f);
|
|
if (!timer_pending(&ring->fence_drv.fallback_timer))
|
|
amdgpu_fence_schedule_fallback(ring);
|
|
FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
|
|
return true;
|
|
}
|
|
|
|
static void amdgpu_fence_release(struct fence *f)
|
|
{
|
|
struct amdgpu_fence *fence = to_amdgpu_fence(f);
|
|
kmem_cache_free(amdgpu_fence_slab, fence);
|
|
}
|
|
|
|
const struct fence_ops amdgpu_fence_ops = {
|
|
.get_driver_name = amdgpu_fence_get_driver_name,
|
|
.get_timeline_name = amdgpu_fence_get_timeline_name,
|
|
.enable_signaling = amdgpu_fence_enable_signaling,
|
|
.signaled = amdgpu_fence_is_signaled,
|
|
.wait = fence_default_wait,
|
|
.release = amdgpu_fence_release,
|
|
};
|
|
|
|
/*
|
|
* Fence debugfs
|
|
*/
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
int i;
|
|
|
|
for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
|
|
struct amdgpu_ring *ring = adev->rings[i];
|
|
if (!ring || !ring->fence_drv.initialized)
|
|
continue;
|
|
|
|
amdgpu_fence_process(ring);
|
|
|
|
seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
|
|
seq_printf(m, "Last signaled fence 0x%016llx\n",
|
|
(unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
|
|
seq_printf(m, "Last emitted 0x%016llx\n",
|
|
ring->fence_drv.sync_seq);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
|
|
*
|
|
* Manually trigger a gpu reset at the next fence wait.
|
|
*/
|
|
static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
seq_printf(m, "gpu reset\n");
|
|
amdgpu_gpu_reset(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_info_list amdgpu_debugfs_fence_list[] = {
|
|
{"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
|
|
{"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
|
|
};
|
|
#endif
|
|
|
|
int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|