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![Alex Deucher](/assets/img/avatar_default.png)
Read back harvest configuration from registers and simplify calculations. No need to program the raster config registers. These are programmed as golden registers and the user mode drivers program them as well. v2: rebase on Tom's patches Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
757 lines
23 KiB
C
757 lines
23 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include <drm/amdgpu_drm.h>
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#include "amdgpu_uvd.h"
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#include "amdgpu_vce.h"
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#include <linux/vga_switcheroo.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include "amdgpu_amdkfd.h"
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#if defined(CONFIG_VGA_SWITCHEROO)
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bool amdgpu_has_atpx(void);
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#else
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static inline bool amdgpu_has_atpx(void) { return false; }
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#endif
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/**
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* amdgpu_driver_unload_kms - Main unload function for KMS.
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*
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* @dev: drm dev pointer
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*
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* This is the main unload function for KMS (all asics).
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* Returns 0 on success.
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*/
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int amdgpu_driver_unload_kms(struct drm_device *dev)
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{
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struct amdgpu_device *adev = dev->dev_private;
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if (adev == NULL)
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return 0;
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if (adev->rmmio == NULL)
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goto done_free;
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pm_runtime_get_sync(dev->dev);
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amdgpu_amdkfd_device_fini(adev);
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amdgpu_acpi_fini(adev);
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amdgpu_device_fini(adev);
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done_free:
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kfree(adev);
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dev->dev_private = NULL;
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return 0;
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}
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/**
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* amdgpu_driver_load_kms - Main load function for KMS.
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*
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* @dev: drm dev pointer
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* @flags: device flags
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*
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* This is the main load function for KMS (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
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{
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struct amdgpu_device *adev;
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int r, acpi_status;
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adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
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if (adev == NULL) {
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return -ENOMEM;
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}
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dev->dev_private = (void *)adev;
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if ((amdgpu_runtime_pm != 0) &&
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amdgpu_has_atpx() &&
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((flags & AMD_IS_APU) == 0))
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flags |= AMD_IS_PX;
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/* amdgpu_device_init should report only fatal error
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* like memory allocation failure or iomapping failure,
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* or memory manager initialization failure, it must
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* properly initialize the GPU MC controller and permit
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* VRAM allocation
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*/
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r = amdgpu_device_init(adev, dev, dev->pdev, flags);
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if (r) {
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dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
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goto out;
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}
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/* Call ACPI methods: require modeset init
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* but failure is not fatal
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*/
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if (!r) {
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acpi_status = amdgpu_acpi_init(adev);
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if (acpi_status)
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dev_dbg(&dev->pdev->dev,
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"Error during ACPI methods call\n");
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}
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amdgpu_amdkfd_load_interface(adev);
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amdgpu_amdkfd_device_probe(adev);
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amdgpu_amdkfd_device_init(adev);
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if (amdgpu_device_is_px(dev)) {
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pm_runtime_use_autosuspend(dev->dev);
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pm_runtime_set_autosuspend_delay(dev->dev, 5000);
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pm_runtime_set_active(dev->dev);
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pm_runtime_allow(dev->dev);
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pm_runtime_mark_last_busy(dev->dev);
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pm_runtime_put_autosuspend(dev->dev);
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}
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out:
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if (r)
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amdgpu_driver_unload_kms(dev);
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return r;
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}
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/*
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* Userspace get information ioctl
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*/
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/**
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* amdgpu_info_ioctl - answer a device specific request.
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*
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* @adev: amdgpu device pointer
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* @data: request object
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* @filp: drm filp
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*
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* This function is used to pass device specific parameters to the userspace
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* drivers. Examples include: pci device id, pipeline parms, tiling params,
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* etc. (all asics).
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* Returns 0 on success, -EINVAL on failure.
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*/
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static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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{
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struct amdgpu_device *adev = dev->dev_private;
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struct drm_amdgpu_info *info = data;
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struct amdgpu_mode_info *minfo = &adev->mode_info;
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void __user *out = (void __user *)(long)info->return_pointer;
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uint32_t size = info->return_size;
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struct drm_crtc *crtc;
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uint32_t ui32 = 0;
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uint64_t ui64 = 0;
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int i, found;
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if (!info->return_size || !info->return_pointer)
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return -EINVAL;
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switch (info->query) {
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case AMDGPU_INFO_ACCEL_WORKING:
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ui32 = adev->accel_working;
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return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
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case AMDGPU_INFO_CRTC_FROM_ID:
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for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
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crtc = (struct drm_crtc *)minfo->crtcs[i];
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if (crtc && crtc->base.id == info->mode_crtc.id) {
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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ui32 = amdgpu_crtc->crtc_id;
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found = 1;
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break;
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}
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}
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if (!found) {
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DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
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return -EINVAL;
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}
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return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
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case AMDGPU_INFO_HW_IP_INFO: {
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struct drm_amdgpu_info_hw_ip ip = {};
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enum amd_ip_block_type type;
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uint32_t ring_mask = 0;
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uint32_t ib_start_alignment = 0;
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uint32_t ib_size_alignment = 0;
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if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
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return -EINVAL;
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switch (info->query_hw_ip.type) {
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case AMDGPU_HW_IP_GFX:
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type = AMD_IP_BLOCK_TYPE_GFX;
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for (i = 0; i < adev->gfx.num_gfx_rings; i++)
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ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
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ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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ib_size_alignment = 8;
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break;
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case AMDGPU_HW_IP_COMPUTE:
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type = AMD_IP_BLOCK_TYPE_GFX;
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for (i = 0; i < adev->gfx.num_compute_rings; i++)
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ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
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ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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ib_size_alignment = 8;
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break;
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case AMDGPU_HW_IP_DMA:
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type = AMD_IP_BLOCK_TYPE_SDMA;
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for (i = 0; i < adev->sdma.num_instances; i++)
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ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
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ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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ib_size_alignment = 1;
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break;
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case AMDGPU_HW_IP_UVD:
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type = AMD_IP_BLOCK_TYPE_UVD;
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ring_mask = adev->uvd.ring.ready ? 1 : 0;
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ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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ib_size_alignment = 8;
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break;
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case AMDGPU_HW_IP_VCE:
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type = AMD_IP_BLOCK_TYPE_VCE;
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for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
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ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
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ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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ib_size_alignment = 8;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (adev->ip_blocks[i].type == type &&
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adev->ip_block_status[i].valid) {
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ip.hw_ip_version_major = adev->ip_blocks[i].major;
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ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
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ip.capabilities_flags = 0;
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ip.available_rings = ring_mask;
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ip.ib_start_alignment = ib_start_alignment;
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ip.ib_size_alignment = ib_size_alignment;
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break;
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}
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}
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return copy_to_user(out, &ip,
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min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
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}
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case AMDGPU_INFO_HW_IP_COUNT: {
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enum amd_ip_block_type type;
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uint32_t count = 0;
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switch (info->query_hw_ip.type) {
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case AMDGPU_HW_IP_GFX:
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type = AMD_IP_BLOCK_TYPE_GFX;
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break;
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case AMDGPU_HW_IP_COMPUTE:
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type = AMD_IP_BLOCK_TYPE_GFX;
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break;
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case AMDGPU_HW_IP_DMA:
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type = AMD_IP_BLOCK_TYPE_SDMA;
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break;
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case AMDGPU_HW_IP_UVD:
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type = AMD_IP_BLOCK_TYPE_UVD;
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break;
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case AMDGPU_HW_IP_VCE:
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type = AMD_IP_BLOCK_TYPE_VCE;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < adev->num_ip_blocks; i++)
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if (adev->ip_blocks[i].type == type &&
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adev->ip_block_status[i].valid &&
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count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
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count++;
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return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
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}
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case AMDGPU_INFO_TIMESTAMP:
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ui64 = amdgpu_asic_get_gpu_clock_counter(adev);
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return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
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case AMDGPU_INFO_FW_VERSION: {
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struct drm_amdgpu_info_firmware fw_info;
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/* We only support one instance of each IP block right now. */
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if (info->query_fw.ip_instance != 0)
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return -EINVAL;
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switch (info->query_fw.fw_type) {
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case AMDGPU_INFO_FW_VCE:
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fw_info.ver = adev->vce.fw_version;
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fw_info.feature = adev->vce.fb_version;
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break;
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case AMDGPU_INFO_FW_UVD:
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fw_info.ver = 0;
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fw_info.feature = 0;
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break;
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case AMDGPU_INFO_FW_GMC:
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fw_info.ver = adev->mc.fw_version;
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fw_info.feature = 0;
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break;
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case AMDGPU_INFO_FW_GFX_ME:
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fw_info.ver = adev->gfx.me_fw_version;
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fw_info.feature = adev->gfx.me_feature_version;
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break;
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case AMDGPU_INFO_FW_GFX_PFP:
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fw_info.ver = adev->gfx.pfp_fw_version;
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fw_info.feature = adev->gfx.pfp_feature_version;
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break;
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case AMDGPU_INFO_FW_GFX_CE:
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fw_info.ver = adev->gfx.ce_fw_version;
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fw_info.feature = adev->gfx.ce_feature_version;
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break;
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case AMDGPU_INFO_FW_GFX_RLC:
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fw_info.ver = adev->gfx.rlc_fw_version;
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fw_info.feature = adev->gfx.rlc_feature_version;
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break;
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case AMDGPU_INFO_FW_GFX_MEC:
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if (info->query_fw.index == 0) {
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fw_info.ver = adev->gfx.mec_fw_version;
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fw_info.feature = adev->gfx.mec_feature_version;
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} else if (info->query_fw.index == 1) {
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fw_info.ver = adev->gfx.mec2_fw_version;
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fw_info.feature = adev->gfx.mec2_feature_version;
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} else
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return -EINVAL;
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break;
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case AMDGPU_INFO_FW_SMC:
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fw_info.ver = adev->pm.fw_version;
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fw_info.feature = 0;
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break;
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case AMDGPU_INFO_FW_SDMA:
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if (info->query_fw.index >= adev->sdma.num_instances)
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return -EINVAL;
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fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version;
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fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version;
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break;
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default:
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return -EINVAL;
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}
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return copy_to_user(out, &fw_info,
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min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
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}
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case AMDGPU_INFO_NUM_BYTES_MOVED:
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ui64 = atomic64_read(&adev->num_bytes_moved);
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return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
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case AMDGPU_INFO_VRAM_USAGE:
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ui64 = atomic64_read(&adev->vram_usage);
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return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
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case AMDGPU_INFO_VIS_VRAM_USAGE:
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ui64 = atomic64_read(&adev->vram_vis_usage);
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return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
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case AMDGPU_INFO_GTT_USAGE:
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ui64 = atomic64_read(&adev->gtt_usage);
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return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
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case AMDGPU_INFO_GDS_CONFIG: {
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struct drm_amdgpu_info_gds gds_info;
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memset(&gds_info, 0, sizeof(gds_info));
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gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
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gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
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gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
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gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
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gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
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gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
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gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
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return copy_to_user(out, &gds_info,
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min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
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}
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case AMDGPU_INFO_VRAM_GTT: {
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struct drm_amdgpu_info_vram_gtt vram_gtt;
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vram_gtt.vram_size = adev->mc.real_vram_size;
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vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
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vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
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vram_gtt.gtt_size = adev->mc.gtt_size;
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vram_gtt.gtt_size -= adev->gart_pin_size;
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return copy_to_user(out, &vram_gtt,
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min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
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}
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case AMDGPU_INFO_READ_MMR_REG: {
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unsigned n, alloc_size;
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uint32_t *regs;
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unsigned se_num = (info->read_mmr_reg.instance >>
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AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
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AMDGPU_INFO_MMR_SE_INDEX_MASK;
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unsigned sh_num = (info->read_mmr_reg.instance >>
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AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
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AMDGPU_INFO_MMR_SH_INDEX_MASK;
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/* set full masks if the userspace set all bits
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* in the bitfields */
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if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
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se_num = 0xffffffff;
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if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
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sh_num = 0xffffffff;
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regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
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if (!regs)
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return -ENOMEM;
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alloc_size = info->read_mmr_reg.count * sizeof(*regs);
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for (i = 0; i < info->read_mmr_reg.count; i++)
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if (amdgpu_asic_read_register(adev, se_num, sh_num,
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info->read_mmr_reg.dword_offset + i,
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®s[i])) {
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DRM_DEBUG_KMS("unallowed offset %#x\n",
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info->read_mmr_reg.dword_offset + i);
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kfree(regs);
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return -EFAULT;
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}
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n = copy_to_user(out, regs, min(size, alloc_size));
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kfree(regs);
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return n ? -EFAULT : 0;
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}
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case AMDGPU_INFO_DEV_INFO: {
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struct drm_amdgpu_info_device dev_info = {};
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struct amdgpu_cu_info cu_info;
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dev_info.device_id = dev->pdev->device;
|
|
dev_info.chip_rev = adev->rev_id;
|
|
dev_info.external_rev = adev->external_rev_id;
|
|
dev_info.pci_rev = dev->pdev->revision;
|
|
dev_info.family = adev->family;
|
|
dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
|
|
dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
|
|
/* return all clocks in KHz */
|
|
dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
|
|
if (adev->pm.dpm_enabled) {
|
|
dev_info.max_engine_clock =
|
|
adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
|
|
dev_info.max_memory_clock =
|
|
adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10;
|
|
} else {
|
|
dev_info.max_engine_clock = adev->pm.default_sclk * 10;
|
|
dev_info.max_memory_clock = adev->pm.default_mclk * 10;
|
|
}
|
|
dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
|
|
dev_info.num_rb_pipes = adev->gfx.config.num_rbs;
|
|
dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
|
|
dev_info._pad = 0;
|
|
dev_info.ids_flags = 0;
|
|
if (adev->flags & AMD_IS_APU)
|
|
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
|
|
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
|
|
dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
|
|
dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
|
|
dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
|
|
AMDGPU_GPU_PAGE_SIZE;
|
|
dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
|
|
|
|
amdgpu_asic_get_cu_info(adev, &cu_info);
|
|
dev_info.cu_active_number = cu_info.number;
|
|
dev_info.cu_ao_mask = cu_info.ao_cu_mask;
|
|
dev_info.ce_ram_size = adev->gfx.ce_ram_size;
|
|
memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
|
|
dev_info.vram_type = adev->mc.vram_type;
|
|
dev_info.vram_bit_width = adev->mc.vram_width;
|
|
dev_info.vce_harvest_config = adev->vce.harvest_config;
|
|
|
|
return copy_to_user(out, &dev_info,
|
|
min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
|
|
}
|
|
default:
|
|
DRM_DEBUG_KMS("Invalid request %d\n", info->query);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Outdated mess for old drm with Xorg being in charge (void function now).
|
|
*/
|
|
/**
|
|
* amdgpu_driver_lastclose_kms - drm callback for last close
|
|
*
|
|
* @dev: drm dev pointer
|
|
*
|
|
* Switch vga_switcheroo state after last close (all asics).
|
|
*/
|
|
void amdgpu_driver_lastclose_kms(struct drm_device *dev)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
amdgpu_fbdev_restore_mode(adev);
|
|
vga_switcheroo_process_delayed_switch();
|
|
}
|
|
|
|
/**
|
|
* amdgpu_driver_open_kms - drm callback for open
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @file_priv: drm file
|
|
*
|
|
* On device open, init vm on cayman+ (all asics).
|
|
* Returns 0 on success, error on failure.
|
|
*/
|
|
int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
struct amdgpu_fpriv *fpriv;
|
|
int r;
|
|
|
|
file_priv->driver_priv = NULL;
|
|
|
|
r = pm_runtime_get_sync(dev->dev);
|
|
if (r < 0)
|
|
return r;
|
|
|
|
fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
|
|
if (unlikely(!fpriv))
|
|
return -ENOMEM;
|
|
|
|
r = amdgpu_vm_init(adev, &fpriv->vm);
|
|
if (r)
|
|
goto error_free;
|
|
|
|
mutex_init(&fpriv->bo_list_lock);
|
|
idr_init(&fpriv->bo_list_handles);
|
|
|
|
amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
|
|
|
|
file_priv->driver_priv = fpriv;
|
|
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
pm_runtime_put_autosuspend(dev->dev);
|
|
return 0;
|
|
|
|
error_free:
|
|
kfree(fpriv);
|
|
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_driver_postclose_kms - drm callback for post close
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @file_priv: drm file
|
|
*
|
|
* On device post close, tear down vm on cayman+ (all asics).
|
|
*/
|
|
void amdgpu_driver_postclose_kms(struct drm_device *dev,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
|
|
struct amdgpu_bo_list *list;
|
|
int handle;
|
|
|
|
if (!fpriv)
|
|
return;
|
|
|
|
amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
|
|
|
|
amdgpu_vm_fini(adev, &fpriv->vm);
|
|
|
|
idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
|
|
amdgpu_bo_list_free(list);
|
|
|
|
idr_destroy(&fpriv->bo_list_handles);
|
|
mutex_destroy(&fpriv->bo_list_lock);
|
|
|
|
kfree(fpriv);
|
|
file_priv->driver_priv = NULL;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_driver_preclose_kms - drm callback for pre close
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @file_priv: drm file
|
|
*
|
|
* On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
|
|
* (all asics).
|
|
*/
|
|
void amdgpu_driver_preclose_kms(struct drm_device *dev,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
amdgpu_uvd_free_handles(adev, file_priv);
|
|
amdgpu_vce_free_handles(adev, file_priv);
|
|
}
|
|
|
|
/*
|
|
* VBlank related functions.
|
|
*/
|
|
/**
|
|
* amdgpu_get_vblank_counter_kms - get frame count
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @pipe: crtc to get the frame count from
|
|
*
|
|
* Gets the frame count on the requested crtc (all asics).
|
|
* Returns frame count on success, -EINVAL on failure.
|
|
*/
|
|
u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
int vpos, hpos, stat;
|
|
u32 count;
|
|
|
|
if (pipe >= adev->mode_info.num_crtc) {
|
|
DRM_ERROR("Invalid crtc %u\n", pipe);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* The hw increments its frame counter at start of vsync, not at start
|
|
* of vblank, as is required by DRM core vblank counter handling.
|
|
* Cook the hw count here to make it appear to the caller as if it
|
|
* incremented at start of vblank. We measure distance to start of
|
|
* vblank in vpos. vpos therefore will be >= 0 between start of vblank
|
|
* and start of vsync, so vpos >= 0 means to bump the hw frame counter
|
|
* result by 1 to give the proper appearance to caller.
|
|
*/
|
|
if (adev->mode_info.crtcs[pipe]) {
|
|
/* Repeat readout if needed to provide stable result if
|
|
* we cross start of vsync during the queries.
|
|
*/
|
|
do {
|
|
count = amdgpu_display_vblank_get_counter(adev, pipe);
|
|
/* Ask amdgpu_get_crtc_scanoutpos to return vpos as
|
|
* distance to start of vblank, instead of regular
|
|
* vertical scanout pos.
|
|
*/
|
|
stat = amdgpu_get_crtc_scanoutpos(
|
|
dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
|
|
&vpos, &hpos, NULL, NULL,
|
|
&adev->mode_info.crtcs[pipe]->base.hwmode);
|
|
} while (count != amdgpu_display_vblank_get_counter(adev, pipe));
|
|
|
|
if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
|
|
(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
|
|
DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
|
|
} else {
|
|
DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
|
|
pipe, vpos);
|
|
|
|
/* Bump counter if we are at >= leading edge of vblank,
|
|
* but before vsync where vpos would turn negative and
|
|
* the hw counter really increments.
|
|
*/
|
|
if (vpos >= 0)
|
|
count++;
|
|
}
|
|
} else {
|
|
/* Fallback to use value as is. */
|
|
count = amdgpu_display_vblank_get_counter(adev, pipe);
|
|
DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
|
|
}
|
|
|
|
return count;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_enable_vblank_kms - enable vblank interrupt
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @pipe: crtc to enable vblank interrupt for
|
|
*
|
|
* Enable the interrupt on the requested crtc (all asics).
|
|
* Returns 0 on success, -EINVAL on failure.
|
|
*/
|
|
int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
|
|
|
|
return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
|
|
}
|
|
|
|
/**
|
|
* amdgpu_disable_vblank_kms - disable vblank interrupt
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @pipe: crtc to disable vblank interrupt for
|
|
*
|
|
* Disable the interrupt on the requested crtc (all asics).
|
|
*/
|
|
void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
|
|
|
|
amdgpu_irq_put(adev, &adev->crtc_irq, idx);
|
|
}
|
|
|
|
/**
|
|
* amdgpu_get_vblank_timestamp_kms - get vblank timestamp
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @crtc: crtc to get the timestamp for
|
|
* @max_error: max error
|
|
* @vblank_time: time value
|
|
* @flags: flags passed to the driver
|
|
*
|
|
* Gets the timestamp on the requested crtc based on the
|
|
* scanout position. (all asics).
|
|
* Returns postive status flags on success, negative error on failure.
|
|
*/
|
|
int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
|
|
int *max_error,
|
|
struct timeval *vblank_time,
|
|
unsigned flags)
|
|
{
|
|
struct drm_crtc *crtc;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
|
|
if (pipe >= dev->num_crtcs) {
|
|
DRM_ERROR("Invalid crtc %u\n", pipe);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Get associated drm_crtc: */
|
|
crtc = &adev->mode_info.crtcs[pipe]->base;
|
|
if (!crtc) {
|
|
/* This can occur on driver load if some component fails to
|
|
* initialize completely and driver is unloaded */
|
|
DRM_ERROR("Uninitialized crtc %d\n", pipe);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Helper routine in DRM core does all the work: */
|
|
return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
|
|
vblank_time, flags,
|
|
&crtc->hwmode);
|
|
}
|
|
|
|
const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
/* KMS */
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
};
|
|
int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
|