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![Christian König](/assets/img/avatar_default.png)
The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making pad_ib a ring function v3: fix typo in macro name Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
476 lines
13 KiB
C
476 lines
13 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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* Christian König
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*/
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "atom.h"
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/*
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* Rings
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* Most engines on the GPU are fed via ring buffers. Ring
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* buffers are areas of GPU accessible memory that the host
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* writes commands into and the GPU reads commands out of.
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* There is a rptr (read pointer) that determines where the
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* GPU is currently reading, and a wptr (write pointer)
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* which determines where the host has written. When the
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* pointers are equal, the ring is idle. When the host
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* writes commands to the ring buffer, it increments the
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* wptr. The GPU then starts fetching commands and executes
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* them until the pointers are equal again.
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*/
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static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring);
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/**
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* amdgpu_ring_alloc - allocate space on the ring buffer
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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* @ndw: number of dwords to allocate in the ring buffer
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*
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* Allocate @ndw dwords in the ring buffer (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
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{
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/* Align requested size with padding so unlock_commit can
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* pad safely */
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ndw = (ndw + ring->align_mask) & ~ring->align_mask;
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/* Make sure we aren't trying to allocate more space
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* than the maximum for one submission
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*/
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if (WARN_ON_ONCE(ndw > ring->max_dw))
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return -ENOMEM;
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ring->count_dw = ndw;
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ring->wptr_old = ring->wptr;
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return 0;
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}
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/** amdgpu_ring_insert_nop - insert NOP packets
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*
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* @ring: amdgpu_ring structure holding ring information
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* @count: the number of NOP packets to insert
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*
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* This is the generic insert_nop function for rings except SDMA
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*/
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void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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amdgpu_ring_write(ring, ring->nop);
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}
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/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
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*
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* @ring: amdgpu_ring structure holding ring information
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* @ib: IB to add NOP packets to
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*
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* This is the generic pad_ib function for rings except SDMA
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*/
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void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
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{
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while (ib->length_dw & ring->align_mask)
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ib->ptr[ib->length_dw++] = ring->nop;
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}
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/**
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* amdgpu_ring_commit - tell the GPU to execute the new
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* commands on the ring buffer
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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*
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* Update the wptr (write pointer) to tell the GPU to
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* execute new commands on the ring buffer (all asics).
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*/
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void amdgpu_ring_commit(struct amdgpu_ring *ring)
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{
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uint32_t count;
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/* We pad to match fetch size */
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count = ring->align_mask + 1 - (ring->wptr & ring->align_mask);
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count %= ring->align_mask + 1;
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ring->funcs->insert_nop(ring, count);
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mb();
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amdgpu_ring_set_wptr(ring);
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}
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/**
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* amdgpu_ring_undo - reset the wptr
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*
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* @ring: amdgpu_ring structure holding ring information
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*
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* Reset the driver's copy of the wptr (all asics).
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*/
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void amdgpu_ring_undo(struct amdgpu_ring *ring)
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{
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ring->wptr = ring->wptr_old;
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}
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/**
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* amdgpu_ring_backup - Back up the content of a ring
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*
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* @ring: the ring we want to back up
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*
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* Saves all unprocessed commits from a ring, returns the number of dwords saved.
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*/
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unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
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uint32_t **data)
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{
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unsigned size, ptr, i;
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*data = NULL;
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if (ring->ring_obj == NULL)
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return 0;
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/* it doesn't make sense to save anything if all fences are signaled */
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if (!amdgpu_fence_count_emitted(ring))
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return 0;
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ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
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size = ring->wptr + (ring->ring_size / 4);
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size -= ptr;
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size &= ring->ptr_mask;
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if (size == 0)
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return 0;
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/* and then save the content of the ring */
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*data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
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if (!*data)
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return 0;
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for (i = 0; i < size; ++i) {
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(*data)[i] = ring->ring[ptr++];
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ptr &= ring->ptr_mask;
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}
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return size;
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}
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/**
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* amdgpu_ring_restore - append saved commands to the ring again
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*
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* @ring: ring to append commands to
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* @size: number of dwords we want to write
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* @data: saved commands
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*
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* Allocates space on the ring and restore the previously saved commands.
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*/
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int amdgpu_ring_restore(struct amdgpu_ring *ring,
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unsigned size, uint32_t *data)
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{
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int i, r;
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if (!size || !data)
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return 0;
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/* restore the saved ring content */
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r = amdgpu_ring_alloc(ring, size);
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if (r)
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return r;
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for (i = 0; i < size; ++i) {
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amdgpu_ring_write(ring, data[i]);
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}
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amdgpu_ring_commit(ring);
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kfree(data);
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return 0;
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}
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/**
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* amdgpu_ring_init - init driver ring struct.
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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* @ring_size: size of the ring
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* @nop: nop packet for this ring
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*
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* Initialize the driver information for the selected ring (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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unsigned ring_size, u32 nop, u32 align_mask,
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struct amdgpu_irq_src *irq_src, unsigned irq_type,
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enum amdgpu_ring_type ring_type)
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{
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u32 rb_bufsz;
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int r;
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if (ring->adev == NULL) {
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if (adev->num_rings >= AMDGPU_MAX_RINGS)
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return -EINVAL;
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ring->adev = adev;
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ring->idx = adev->num_rings++;
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adev->rings[ring->idx] = ring;
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r = amdgpu_fence_driver_init_ring(ring);
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if (r)
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return r;
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}
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r = amdgpu_wb_get(adev, &ring->rptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_wb_get(adev, &ring->wptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_wb_get(adev, &ring->fence_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_wb_get(adev, &ring->next_rptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r);
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return r;
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}
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ring->next_rptr_gpu_addr = adev->wb.gpu_addr + (ring->next_rptr_offs * 4);
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ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs];
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spin_lock_init(&ring->fence_lock);
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r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
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if (r) {
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dev_err(adev->dev, "failed initializing fences (%d).\n", r);
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return r;
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}
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/* Align ring size */
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rb_bufsz = order_base_2(ring_size / 8);
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ring_size = (1 << (rb_bufsz + 1)) * 4;
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ring->ring_size = ring_size;
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ring->align_mask = align_mask;
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ring->nop = nop;
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ring->type = ring_type;
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/* Allocate ring buffer */
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if (ring->ring_obj == NULL) {
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r = amdgpu_bo_create(adev, ring->ring_size, PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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NULL, NULL, &ring->ring_obj);
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if (r) {
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dev_err(adev->dev, "(%d) ring create failed\n", r);
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return r;
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}
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r = amdgpu_bo_reserve(ring->ring_obj, false);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_pin(ring->ring_obj, AMDGPU_GEM_DOMAIN_GTT,
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&ring->gpu_addr);
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if (r) {
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amdgpu_bo_unreserve(ring->ring_obj);
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dev_err(adev->dev, "(%d) ring pin failed\n", r);
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return r;
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}
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r = amdgpu_bo_kmap(ring->ring_obj,
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(void **)&ring->ring);
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amdgpu_bo_unreserve(ring->ring_obj);
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if (r) {
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dev_err(adev->dev, "(%d) ring map failed\n", r);
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return r;
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}
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}
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ring->ptr_mask = (ring->ring_size / 4) - 1;
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ring->max_dw = DIV_ROUND_UP(ring->ring_size / 4,
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amdgpu_sched_hw_submission);
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if (amdgpu_debugfs_ring_init(adev, ring)) {
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DRM_ERROR("Failed to register debugfs file for rings !\n");
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}
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return 0;
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}
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/**
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* amdgpu_ring_fini - tear down the driver ring struct.
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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*
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* Tear down the driver information for the selected ring (all asics).
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*/
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void amdgpu_ring_fini(struct amdgpu_ring *ring)
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{
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int r;
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struct amdgpu_bo *ring_obj;
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ring_obj = ring->ring_obj;
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ring->ready = false;
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ring->ring = NULL;
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ring->ring_obj = NULL;
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amdgpu_wb_free(ring->adev, ring->fence_offs);
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amdgpu_wb_free(ring->adev, ring->rptr_offs);
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amdgpu_wb_free(ring->adev, ring->wptr_offs);
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amdgpu_wb_free(ring->adev, ring->next_rptr_offs);
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if (ring_obj) {
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r = amdgpu_bo_reserve(ring_obj, false);
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if (likely(r == 0)) {
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amdgpu_bo_kunmap(ring_obj);
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amdgpu_bo_unpin(ring_obj);
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amdgpu_bo_unreserve(ring_obj);
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}
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amdgpu_bo_unref(&ring_obj);
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}
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}
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/**
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* amdgpu_ring_from_fence - get ring from fence
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*
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* @f: fence structure
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*
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* Extract the ring a fence belongs to. Handles both scheduler as
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* well as hardware fences.
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*/
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struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f)
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{
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struct amdgpu_fence *a_fence;
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struct amd_sched_fence *s_fence;
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s_fence = to_amd_sched_fence(f);
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if (s_fence)
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return container_of(s_fence->sched, struct amdgpu_ring, sched);
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a_fence = to_amdgpu_fence(f);
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if (a_fence)
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return a_fence->ring;
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return NULL;
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct amdgpu_device *adev = dev->dev_private;
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int roffset = *(int*)node->info_ent->data;
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struct amdgpu_ring *ring = (void *)(((uint8_t*)adev) + roffset);
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uint32_t rptr, wptr, rptr_next;
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unsigned i;
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wptr = amdgpu_ring_get_wptr(ring);
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seq_printf(m, "wptr: 0x%08x [%5d]\n", wptr, wptr);
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rptr = amdgpu_ring_get_rptr(ring);
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rptr_next = le32_to_cpu(*ring->next_rptr_cpu_addr);
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seq_printf(m, "rptr: 0x%08x [%5d]\n", rptr, rptr);
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seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",
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ring->wptr, ring->wptr);
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if (!ring->ready)
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return 0;
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/* print 8 dw before current rptr as often it's the last executed
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* packet that is the root issue
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*/
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i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
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while (i != rptr) {
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seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
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if (i == rptr)
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seq_puts(m, " *");
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if (i == rptr_next)
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seq_puts(m, " #");
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seq_puts(m, "\n");
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i = (i + 1) & ring->ptr_mask;
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}
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while (i != wptr) {
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seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);
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if (i == rptr)
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seq_puts(m, " *");
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if (i == rptr_next)
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seq_puts(m, " #");
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seq_puts(m, "\n");
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i = (i + 1) & ring->ptr_mask;
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}
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return 0;
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}
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/* TODO: clean this up !*/
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static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]);
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static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]);
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static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]);
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static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma.instance[0].ring);
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static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma.instance[1].ring);
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static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring);
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static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]);
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static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]);
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static struct drm_info_list amdgpu_debugfs_ring_info_list[] = {
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{"amdgpu_ring_gfx", amdgpu_debugfs_ring_info, 0, &amdgpu_gfx_index},
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{"amdgpu_ring_cp1", amdgpu_debugfs_ring_info, 0, &cayman_cp1_index},
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{"amdgpu_ring_cp2", amdgpu_debugfs_ring_info, 0, &cayman_cp2_index},
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{"amdgpu_ring_dma1", amdgpu_debugfs_ring_info, 0, &amdgpu_dma1_index},
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{"amdgpu_ring_dma2", amdgpu_debugfs_ring_info, 0, &amdgpu_dma2_index},
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{"amdgpu_ring_uvd", amdgpu_debugfs_ring_info, 0, &r600_uvd_index},
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{"amdgpu_ring_vce1", amdgpu_debugfs_ring_info, 0, &si_vce1_index},
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{"amdgpu_ring_vce2", amdgpu_debugfs_ring_info, 0, &si_vce2_index},
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};
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#endif
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static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring)
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{
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#if defined(CONFIG_DEBUG_FS)
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unsigned i;
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for (i = 0; i < ARRAY_SIZE(amdgpu_debugfs_ring_info_list); ++i) {
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struct drm_info_list *info = &amdgpu_debugfs_ring_info_list[i];
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int roffset = *(int*)amdgpu_debugfs_ring_info_list[i].data;
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struct amdgpu_ring *other = (void *)(((uint8_t*)adev) + roffset);
|
|
unsigned r;
|
|
|
|
if (other != ring)
|
|
continue;
|
|
|
|
r = amdgpu_debugfs_add_files(adev, info, 1);
|
|
if (r)
|
|
return r;
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|