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![Max Filippov](/assets/img/avatar_default.png)
This allows using OpenCores I2C controller attached to its host in native-endian mode with bi-endian CPUs. Example of such system is Xtensa XTFPGA platform. Acked-by: Peter Korsgaard <peter@korsgaard.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
584 lines
14 KiB
C
584 lines
14 KiB
C
/*
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* i2c-ocores.c: I2C bus driver for OpenCores I2C controller
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* (http://www.opencores.org/projects.cgi/web/i2c/overview).
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*
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* Peter Korsgaard <jacmet@sunsite.dk>
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*
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* Support for the GRLIB port of the controller by
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* Andreas Larsson <andreas@gaisler.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/wait.h>
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#include <linux/i2c-ocores.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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struct ocores_i2c {
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void __iomem *base;
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u32 reg_shift;
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u32 reg_io_width;
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wait_queue_head_t wait;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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int pos;
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int nmsgs;
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int state; /* see STATE_ */
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struct clk *clk;
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int ip_clock_khz;
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int bus_clock_khz;
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void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
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u8 (*getreg)(struct ocores_i2c *i2c, int reg);
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};
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/* registers */
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#define OCI2C_PRELOW 0
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#define OCI2C_PREHIGH 1
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#define OCI2C_CONTROL 2
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#define OCI2C_DATA 3
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#define OCI2C_CMD 4 /* write only */
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#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
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#define OCI2C_CTRL_IEN 0x40
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#define OCI2C_CTRL_EN 0x80
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#define OCI2C_CMD_START 0x91
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#define OCI2C_CMD_STOP 0x41
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#define OCI2C_CMD_READ 0x21
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#define OCI2C_CMD_WRITE 0x11
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#define OCI2C_CMD_READ_ACK 0x21
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#define OCI2C_CMD_READ_NACK 0x29
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#define OCI2C_CMD_IACK 0x01
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#define OCI2C_STAT_IF 0x01
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#define OCI2C_STAT_TIP 0x02
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#define OCI2C_STAT_ARBLOST 0x20
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#define OCI2C_STAT_BUSY 0x40
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#define OCI2C_STAT_NACK 0x80
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#define STATE_DONE 0
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#define STATE_START 1
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#define STATE_WRITE 2
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#define STATE_READ 3
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#define STATE_ERROR 4
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#define TYPE_OCORES 0
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#define TYPE_GRLIB 1
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static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite8(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite16(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite32(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
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}
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static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
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{
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iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
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{
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return ioread8(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
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{
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return ioread16(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
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{
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return ioread32(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
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{
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return ioread16be(i2c->base + (reg << i2c->reg_shift));
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}
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static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
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{
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return ioread32be(i2c->base + (reg << i2c->reg_shift));
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}
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static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
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{
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i2c->setreg(i2c, reg, value);
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}
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static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
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{
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return i2c->getreg(i2c, reg);
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}
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static void ocores_process(struct ocores_i2c *i2c)
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{
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struct i2c_msg *msg = i2c->msg;
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u8 stat = oc_getreg(i2c, OCI2C_STATUS);
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if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
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/* stop has been sent */
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
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wake_up(&i2c->wait);
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return;
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}
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/* error? */
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if (stat & OCI2C_STAT_ARBLOST) {
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i2c->state = STATE_ERROR;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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return;
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}
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if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
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i2c->state =
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(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
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if (stat & OCI2C_STAT_NACK) {
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i2c->state = STATE_ERROR;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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return;
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}
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} else
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msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
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/* end of msg? */
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if (i2c->pos == msg->len) {
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i2c->nmsgs--;
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i2c->msg++;
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i2c->pos = 0;
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msg = i2c->msg;
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if (i2c->nmsgs) { /* end? */
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/* send start? */
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if (!(msg->flags & I2C_M_NOSTART)) {
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u8 addr = (msg->addr << 1);
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if (msg->flags & I2C_M_RD)
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addr |= 1;
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i2c->state = STATE_START;
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oc_setreg(i2c, OCI2C_DATA, addr);
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
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return;
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} else
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i2c->state = (msg->flags & I2C_M_RD)
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? STATE_READ : STATE_WRITE;
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} else {
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i2c->state = STATE_DONE;
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
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return;
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}
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}
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if (i2c->state == STATE_READ) {
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oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
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OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
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} else {
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oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
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}
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}
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static irqreturn_t ocores_isr(int irq, void *dev_id)
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{
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struct ocores_i2c *i2c = dev_id;
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ocores_process(i2c);
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return IRQ_HANDLED;
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}
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static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
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{
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struct ocores_i2c *i2c = i2c_get_adapdata(adap);
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i2c->msg = msgs;
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i2c->pos = 0;
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i2c->nmsgs = num;
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i2c->state = STATE_START;
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oc_setreg(i2c, OCI2C_DATA,
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(i2c->msg->addr << 1) |
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((i2c->msg->flags & I2C_M_RD) ? 1:0));
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
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if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
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(i2c->state == STATE_DONE), HZ))
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return (i2c->state == STATE_DONE) ? num : -EIO;
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else
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return -ETIMEDOUT;
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}
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static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
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{
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int prescale;
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int diff;
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u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
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/* make sure the device is disabled */
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oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
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prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
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prescale = clamp(prescale, 0, 0xffff);
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diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
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if (abs(diff) > i2c->bus_clock_khz / 10) {
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dev_err(dev,
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"Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
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i2c->ip_clock_khz, i2c->bus_clock_khz);
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return -EINVAL;
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}
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oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
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oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
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/* Init the device */
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
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oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
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return 0;
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}
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static u32 ocores_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm ocores_algorithm = {
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.master_xfer = ocores_xfer,
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.functionality = ocores_func,
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};
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static struct i2c_adapter ocores_adapter = {
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.owner = THIS_MODULE,
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.name = "i2c-ocores",
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.class = I2C_CLASS_DEPRECATED,
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.algo = &ocores_algorithm,
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};
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static const struct of_device_id ocores_i2c_match[] = {
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{
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.compatible = "opencores,i2c-ocores",
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.data = (void *)TYPE_OCORES,
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},
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{
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.compatible = "aeroflexgaisler,i2cmst",
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.data = (void *)TYPE_GRLIB,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, ocores_i2c_match);
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#ifdef CONFIG_OF
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/* Read and write functions for the GRLIB port of the controller. Registers are
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* 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
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* register. The subsequent registers has their offset decreased accordingly. */
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static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
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{
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u32 rd;
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int rreg = reg;
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if (reg != OCI2C_PRELOW)
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rreg--;
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rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
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if (reg == OCI2C_PREHIGH)
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return (u8)(rd >> 8);
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else
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return (u8)rd;
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}
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static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
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{
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u32 curr, wr;
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int rreg = reg;
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if (reg != OCI2C_PRELOW)
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rreg--;
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if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
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curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
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if (reg == OCI2C_PRELOW)
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wr = (curr & 0xff00) | value;
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else
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wr = (((u32)value) << 8) | (curr & 0xff);
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} else {
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wr = value;
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}
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iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
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}
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static int ocores_i2c_of_probe(struct platform_device *pdev,
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struct ocores_i2c *i2c)
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{
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struct device_node *np = pdev->dev.of_node;
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const struct of_device_id *match;
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u32 val;
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u32 clock_frequency;
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bool clock_frequency_present;
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if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
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/* no 'reg-shift', check for deprecated 'regstep' */
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if (!of_property_read_u32(np, "regstep", &val)) {
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if (!is_power_of_2(val)) {
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dev_err(&pdev->dev, "invalid regstep %d\n",
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val);
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return -EINVAL;
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}
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i2c->reg_shift = ilog2(val);
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dev_warn(&pdev->dev,
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"regstep property deprecated, use reg-shift\n");
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}
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}
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clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
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&clock_frequency);
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i2c->bus_clock_khz = 100;
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i2c->clk = devm_clk_get(&pdev->dev, NULL);
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if (!IS_ERR(i2c->clk)) {
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int ret = clk_prepare_enable(i2c->clk);
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if (ret) {
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dev_err(&pdev->dev,
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"clk_prepare_enable failed: %d\n", ret);
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return ret;
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}
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i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
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if (clock_frequency_present)
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i2c->bus_clock_khz = clock_frequency / 1000;
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}
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if (i2c->ip_clock_khz == 0) {
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if (of_property_read_u32(np, "opencores,ip-clock-frequency",
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&val)) {
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if (!clock_frequency_present) {
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dev_err(&pdev->dev,
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"Missing required parameter 'opencores,ip-clock-frequency'\n");
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return -ENODEV;
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}
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i2c->ip_clock_khz = clock_frequency / 1000;
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dev_warn(&pdev->dev,
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"Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
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} else {
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i2c->ip_clock_khz = val / 1000;
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if (clock_frequency_present)
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i2c->bus_clock_khz = clock_frequency / 1000;
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}
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}
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of_property_read_u32(pdev->dev.of_node, "reg-io-width",
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&i2c->reg_io_width);
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match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
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if (match && (long)match->data == TYPE_GRLIB) {
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dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
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i2c->setreg = oc_setreg_grlib;
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i2c->getreg = oc_getreg_grlib;
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}
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return 0;
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}
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#else
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#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
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#endif
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static int ocores_i2c_probe(struct platform_device *pdev)
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{
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struct ocores_i2c *i2c;
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struct ocores_i2c_platform_data *pdata;
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struct resource *res;
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int irq;
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int ret;
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int i;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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i2c->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(i2c->base))
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return PTR_ERR(i2c->base);
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pdata = dev_get_platdata(&pdev->dev);
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if (pdata) {
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i2c->reg_shift = pdata->reg_shift;
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i2c->reg_io_width = pdata->reg_io_width;
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i2c->ip_clock_khz = pdata->clock_khz;
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i2c->bus_clock_khz = 100;
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} else {
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ret = ocores_i2c_of_probe(pdev, i2c);
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if (ret)
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return ret;
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}
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if (i2c->reg_io_width == 0)
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i2c->reg_io_width = 1; /* Set to default value */
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if (!i2c->setreg || !i2c->getreg) {
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bool be = pdata ? pdata->big_endian :
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of_device_is_big_endian(pdev->dev.of_node);
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switch (i2c->reg_io_width) {
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case 1:
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i2c->setreg = oc_setreg_8;
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i2c->getreg = oc_getreg_8;
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break;
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case 2:
|
|
i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
|
|
i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
|
|
break;
|
|
|
|
case 4:
|
|
i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
|
|
i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
|
|
break;
|
|
|
|
default:
|
|
dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
|
|
i2c->reg_io_width);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
ret = ocores_init(&pdev->dev, i2c);
|
|
if (ret)
|
|
return ret;
|
|
|
|
init_waitqueue_head(&i2c->wait);
|
|
ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
|
|
pdev->name, i2c);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Cannot claim IRQ\n");
|
|
return ret;
|
|
}
|
|
|
|
/* hook up driver to tree */
|
|
platform_set_drvdata(pdev, i2c);
|
|
i2c->adap = ocores_adapter;
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
|
i2c->adap.dev.parent = &pdev->dev;
|
|
i2c->adap.dev.of_node = pdev->dev.of_node;
|
|
|
|
/* add i2c adapter to i2c tree */
|
|
ret = i2c_add_adapter(&i2c->adap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to add adapter\n");
|
|
return ret;
|
|
}
|
|
|
|
/* add in known devices to the bus */
|
|
if (pdata) {
|
|
for (i = 0; i < pdata->num_devices; i++)
|
|
i2c_new_device(&i2c->adap, pdata->devices + i);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ocores_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct ocores_i2c *i2c = platform_get_drvdata(pdev);
|
|
|
|
/* disable i2c logic */
|
|
oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
|
|
& ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
|
|
|
|
/* remove adapter & data */
|
|
i2c_del_adapter(&i2c->adap);
|
|
|
|
if (!IS_ERR(i2c->clk))
|
|
clk_disable_unprepare(i2c->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int ocores_i2c_suspend(struct device *dev)
|
|
{
|
|
struct ocores_i2c *i2c = dev_get_drvdata(dev);
|
|
u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
|
|
|
|
/* make sure the device is disabled */
|
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
|
|
|
|
if (!IS_ERR(i2c->clk))
|
|
clk_disable_unprepare(i2c->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int ocores_i2c_resume(struct device *dev)
|
|
{
|
|
struct ocores_i2c *i2c = dev_get_drvdata(dev);
|
|
|
|
if (!IS_ERR(i2c->clk)) {
|
|
unsigned long rate;
|
|
int ret = clk_prepare_enable(i2c->clk);
|
|
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"clk_prepare_enable failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
rate = clk_get_rate(i2c->clk) / 1000;
|
|
if (rate)
|
|
i2c->ip_clock_khz = rate;
|
|
}
|
|
return ocores_init(dev, i2c);
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
|
|
#define OCORES_I2C_PM (&ocores_i2c_pm)
|
|
#else
|
|
#define OCORES_I2C_PM NULL
|
|
#endif
|
|
|
|
static struct platform_driver ocores_i2c_driver = {
|
|
.probe = ocores_i2c_probe,
|
|
.remove = ocores_i2c_remove,
|
|
.driver = {
|
|
.name = "ocores-i2c",
|
|
.of_match_table = ocores_i2c_match,
|
|
.pm = OCORES_I2C_PM,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(ocores_i2c_driver);
|
|
|
|
MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
|
|
MODULE_DESCRIPTION("OpenCores I2C bus driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:ocores-i2c");
|