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![Vincent Wan](/assets/img/avatar_default.png)
Change AMD CZ SMBUS device ID from 0x790b to use Macro definition Signed-off-by: Wan ZongShun <Vincent.Wan@amd.com> Acked-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Jean Delvare <jdelvare@suse.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
700 lines
19 KiB
C
700 lines
19 KiB
C
/*
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Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
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Philip Edelbrock <phil@netroedge.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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*/
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/*
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Supports:
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Intel PIIX4, 440MX
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Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
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ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
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AMD Hudson-2, ML, CZ
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SMSC Victory66
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Note: we assume there can only be one device, with one or more
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SMBus interfaces.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/stddef.h>
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#include <linux/ioport.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/dmi.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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/* PIIX4 SMBus address offsets */
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#define SMBHSTSTS (0 + piix4_smba)
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#define SMBHSLVSTS (1 + piix4_smba)
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#define SMBHSTCNT (2 + piix4_smba)
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#define SMBHSTCMD (3 + piix4_smba)
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#define SMBHSTADD (4 + piix4_smba)
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#define SMBHSTDAT0 (5 + piix4_smba)
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#define SMBHSTDAT1 (6 + piix4_smba)
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#define SMBBLKDAT (7 + piix4_smba)
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#define SMBSLVCNT (8 + piix4_smba)
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#define SMBSHDWCMD (9 + piix4_smba)
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#define SMBSLVEVT (0xA + piix4_smba)
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#define SMBSLVDAT (0xC + piix4_smba)
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/* count for request_region */
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#define SMBIOSIZE 8
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/* PCI Address Constants */
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#define SMBBA 0x090
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#define SMBHSTCFG 0x0D2
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#define SMBSLVC 0x0D3
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#define SMBSHDW1 0x0D4
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#define SMBSHDW2 0x0D5
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#define SMBREV 0x0D6
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/* Other settings */
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#define MAX_TIMEOUT 500
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#define ENABLE_INT9 0
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/* PIIX4 constants */
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#define PIIX4_QUICK 0x00
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#define PIIX4_BYTE 0x04
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#define PIIX4_BYTE_DATA 0x08
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#define PIIX4_WORD_DATA 0x0C
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#define PIIX4_BLOCK_DATA 0x14
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/* insmod parameters */
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/* If force is set to anything different from 0, we forcibly enable the
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PIIX4. DANGEROUS! */
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static int force;
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module_param (force, int, 0);
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MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
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/* If force_addr is set to anything different from 0, we forcibly enable
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the PIIX4 at the given address. VERY DANGEROUS! */
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static int force_addr;
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module_param (force_addr, int, 0);
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MODULE_PARM_DESC(force_addr,
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"Forcibly enable the PIIX4 at the given address. "
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"EXTREMELY DANGEROUS!");
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static int srvrworks_csb5_delay;
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static struct pci_driver piix4_driver;
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static const struct dmi_system_id piix4_dmi_blacklist[] = {
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{
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.ident = "Sapphire AM2RD790",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
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DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
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},
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},
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{
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.ident = "DFI Lanparty UT 790FX",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
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DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
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},
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},
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{ }
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};
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/* The IBM entry is in a separate table because we only check it
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on Intel-based systems */
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static const struct dmi_system_id piix4_dmi_ibm[] = {
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{
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.ident = "IBM",
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.matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
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},
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{ },
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};
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struct i2c_piix4_adapdata {
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unsigned short smba;
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};
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static int piix4_setup(struct pci_dev *PIIX4_dev,
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const struct pci_device_id *id)
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{
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unsigned char temp;
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unsigned short piix4_smba;
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if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
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(PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
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srvrworks_csb5_delay = 1;
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/* On some motherboards, it was reported that accessing the SMBus
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caused severe hardware problems */
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if (dmi_check_system(piix4_dmi_blacklist)) {
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dev_err(&PIIX4_dev->dev,
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"Accessing the SMBus on this system is unsafe!\n");
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return -EPERM;
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}
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/* Don't access SMBus on IBM systems which get corrupted eeproms */
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if (dmi_check_system(piix4_dmi_ibm) &&
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PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
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dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
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"may corrupt your serial eeprom! Refusing to load "
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"module!\n");
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return -EPERM;
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}
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/* Determine the address of the SMBus areas */
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if (force_addr) {
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piix4_smba = force_addr & 0xfff0;
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force = 0;
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} else {
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pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
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piix4_smba &= 0xfff0;
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if(piix4_smba == 0) {
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dev_err(&PIIX4_dev->dev, "SMBus base address "
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"uninitialized - upgrade BIOS or use "
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"force_addr=0xaddr\n");
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return -ENODEV;
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}
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}
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if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
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return -ENODEV;
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if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
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dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
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piix4_smba);
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return -EBUSY;
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}
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pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
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/* If force_addr is set, we program the new address here. Just to make
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sure, we disable the PIIX4 first. */
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if (force_addr) {
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pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
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pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
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pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
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dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
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"new address %04x!\n", piix4_smba);
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} else if ((temp & 1) == 0) {
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if (force) {
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/* This should never need to be done, but has been
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* noted that many Dell machines have the SMBus
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* interface on the PIIX4 disabled!? NOTE: This assumes
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* I/O space and other allocations WERE done by the
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* Bios! Don't complain if your hardware does weird
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* things after enabling this. :') Check for Bios
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* updates before resorting to this.
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*/
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pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
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temp | 1);
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dev_notice(&PIIX4_dev->dev,
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"WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
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} else {
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dev_err(&PIIX4_dev->dev,
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"SMBus Host Controller not enabled!\n");
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release_region(piix4_smba, SMBIOSIZE);
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return -ENODEV;
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}
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}
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if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
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dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
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else if ((temp & 0x0E) == 0)
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dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
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else
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dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
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"(or code out of date)!\n");
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pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
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dev_info(&PIIX4_dev->dev,
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"SMBus Host Controller at 0x%x, revision %d\n",
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piix4_smba, temp);
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return piix4_smba;
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}
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static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
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const struct pci_device_id *id, u8 aux)
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{
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unsigned short piix4_smba;
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unsigned short smba_idx = 0xcd6;
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u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status;
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u8 i2ccfg, i2ccfg_offset = 0x10;
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/* SB800 and later SMBus does not support forcing address */
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if (force || force_addr) {
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dev_err(&PIIX4_dev->dev, "SMBus does not support "
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"forcing address!\n");
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return -EINVAL;
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}
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/* Determine the address of the SMBus areas */
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if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
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PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
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PIIX4_dev->revision >= 0x41) ||
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(PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
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PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
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PIIX4_dev->revision >= 0x49))
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smb_en = 0x00;
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else
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smb_en = (aux) ? 0x28 : 0x2c;
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if (!request_region(smba_idx, 2, "smba_idx")) {
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dev_err(&PIIX4_dev->dev, "SMBus base address index region "
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"0x%x already in use!\n", smba_idx);
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return -EBUSY;
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}
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outb_p(smb_en, smba_idx);
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smba_en_lo = inb_p(smba_idx + 1);
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outb_p(smb_en + 1, smba_idx);
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smba_en_hi = inb_p(smba_idx + 1);
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release_region(smba_idx, 2);
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if (!smb_en) {
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smb_en_status = smba_en_lo & 0x10;
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piix4_smba = smba_en_hi << 8;
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if (aux)
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piix4_smba |= 0x20;
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} else {
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smb_en_status = smba_en_lo & 0x01;
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piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
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}
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if (!smb_en_status) {
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dev_err(&PIIX4_dev->dev,
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"SMBus Host Controller not enabled!\n");
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return -ENODEV;
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}
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if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
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return -ENODEV;
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if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
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dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
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piix4_smba);
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return -EBUSY;
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}
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/* Aux SMBus does not support IRQ information */
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if (aux) {
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dev_info(&PIIX4_dev->dev,
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"Auxiliary SMBus Host Controller at 0x%x\n",
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piix4_smba);
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return piix4_smba;
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}
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/* Request the SMBus I2C bus config region */
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if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
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dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
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"0x%x already in use!\n", piix4_smba + i2ccfg_offset);
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release_region(piix4_smba, SMBIOSIZE);
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return -EBUSY;
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}
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i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
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release_region(piix4_smba + i2ccfg_offset, 1);
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if (i2ccfg & 1)
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dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
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else
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dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
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dev_info(&PIIX4_dev->dev,
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"SMBus Host Controller at 0x%x, revision %d\n",
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piix4_smba, i2ccfg >> 4);
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return piix4_smba;
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}
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static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
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const struct pci_device_id *id,
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unsigned short base_reg_addr)
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{
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/* Set up auxiliary SMBus controllers found on some
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* AMD chipsets e.g. SP5100 (SB700 derivative) */
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unsigned short piix4_smba;
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/* Read address of auxiliary SMBus controller */
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pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
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if ((piix4_smba & 1) == 0) {
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dev_dbg(&PIIX4_dev->dev,
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"Auxiliary SMBus controller not enabled\n");
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return -ENODEV;
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}
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piix4_smba &= 0xfff0;
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if (piix4_smba == 0) {
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dev_dbg(&PIIX4_dev->dev,
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"Auxiliary SMBus base address uninitialized\n");
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return -ENODEV;
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}
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if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
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return -ENODEV;
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if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
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dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
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"already in use!\n", piix4_smba);
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return -EBUSY;
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}
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dev_info(&PIIX4_dev->dev,
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"Auxiliary SMBus Host Controller at 0x%x\n",
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piix4_smba);
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return piix4_smba;
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}
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static int piix4_transaction(struct i2c_adapter *piix4_adapter)
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{
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struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
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unsigned short piix4_smba = adapdata->smba;
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int temp;
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int result = 0;
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int timeout = 0;
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dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
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"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
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inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
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inb_p(SMBHSTDAT1));
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/* Make sure the SMBus host is ready to start transmitting */
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if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
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dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
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"Resetting...\n", temp);
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outb_p(temp, SMBHSTSTS);
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if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
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dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
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return -EBUSY;
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} else {
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dev_dbg(&piix4_adapter->dev, "Successful!\n");
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}
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}
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/* start the transaction by setting bit 6 */
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outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
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/* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
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if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
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msleep(2);
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else
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msleep(1);
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while ((++timeout < MAX_TIMEOUT) &&
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((temp = inb_p(SMBHSTSTS)) & 0x01))
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msleep(1);
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/* If the SMBus is still busy, we give up */
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if (timeout == MAX_TIMEOUT) {
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dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
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result = -ETIMEDOUT;
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}
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if (temp & 0x10) {
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result = -EIO;
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dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
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}
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if (temp & 0x08) {
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result = -EIO;
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dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
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"locked until next hard reset. (sorry!)\n");
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/* Clock stops and slave is stuck in mid-transmission */
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}
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if (temp & 0x04) {
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result = -ENXIO;
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dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
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}
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if (inb_p(SMBHSTSTS) != 0x00)
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outb_p(inb(SMBHSTSTS), SMBHSTSTS);
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if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
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dev_err(&piix4_adapter->dev, "Failed reset at end of "
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"transaction (%02x)\n", temp);
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}
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dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
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"ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
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inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
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inb_p(SMBHSTDAT1));
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return result;
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}
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/* Return negative errno on error. */
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static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
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unsigned short flags, char read_write,
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u8 command, int size, union i2c_smbus_data * data)
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{
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|
struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
|
|
unsigned short piix4_smba = adapdata->smba;
|
|
int i, len;
|
|
int status;
|
|
|
|
switch (size) {
|
|
case I2C_SMBUS_QUICK:
|
|
outb_p((addr << 1) | read_write,
|
|
SMBHSTADD);
|
|
size = PIIX4_QUICK;
|
|
break;
|
|
case I2C_SMBUS_BYTE:
|
|
outb_p((addr << 1) | read_write,
|
|
SMBHSTADD);
|
|
if (read_write == I2C_SMBUS_WRITE)
|
|
outb_p(command, SMBHSTCMD);
|
|
size = PIIX4_BYTE;
|
|
break;
|
|
case I2C_SMBUS_BYTE_DATA:
|
|
outb_p((addr << 1) | read_write,
|
|
SMBHSTADD);
|
|
outb_p(command, SMBHSTCMD);
|
|
if (read_write == I2C_SMBUS_WRITE)
|
|
outb_p(data->byte, SMBHSTDAT0);
|
|
size = PIIX4_BYTE_DATA;
|
|
break;
|
|
case I2C_SMBUS_WORD_DATA:
|
|
outb_p((addr << 1) | read_write,
|
|
SMBHSTADD);
|
|
outb_p(command, SMBHSTCMD);
|
|
if (read_write == I2C_SMBUS_WRITE) {
|
|
outb_p(data->word & 0xff, SMBHSTDAT0);
|
|
outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
|
|
}
|
|
size = PIIX4_WORD_DATA;
|
|
break;
|
|
case I2C_SMBUS_BLOCK_DATA:
|
|
outb_p((addr << 1) | read_write,
|
|
SMBHSTADD);
|
|
outb_p(command, SMBHSTCMD);
|
|
if (read_write == I2C_SMBUS_WRITE) {
|
|
len = data->block[0];
|
|
if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
|
|
return -EINVAL;
|
|
outb_p(len, SMBHSTDAT0);
|
|
i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
|
|
for (i = 1; i <= len; i++)
|
|
outb_p(data->block[i], SMBBLKDAT);
|
|
}
|
|
size = PIIX4_BLOCK_DATA;
|
|
break;
|
|
default:
|
|
dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
|
|
|
|
status = piix4_transaction(adap);
|
|
if (status)
|
|
return status;
|
|
|
|
if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
|
|
return 0;
|
|
|
|
|
|
switch (size) {
|
|
case PIIX4_BYTE:
|
|
case PIIX4_BYTE_DATA:
|
|
data->byte = inb_p(SMBHSTDAT0);
|
|
break;
|
|
case PIIX4_WORD_DATA:
|
|
data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
|
|
break;
|
|
case PIIX4_BLOCK_DATA:
|
|
data->block[0] = inb_p(SMBHSTDAT0);
|
|
if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
|
|
return -EPROTO;
|
|
i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
|
|
for (i = 1; i <= data->block[0]; i++)
|
|
data->block[i] = inb_p(SMBBLKDAT);
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static u32 piix4_func(struct i2c_adapter *adapter)
|
|
{
|
|
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
|
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
|
I2C_FUNC_SMBUS_BLOCK_DATA;
|
|
}
|
|
|
|
static const struct i2c_algorithm smbus_algorithm = {
|
|
.smbus_xfer = piix4_access,
|
|
.functionality = piix4_func,
|
|
};
|
|
|
|
static const struct pci_device_id piix4_ids[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
|
|
PCI_DEVICE_ID_SERVERWORKS_OSB4) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
|
|
PCI_DEVICE_ID_SERVERWORKS_CSB5) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
|
|
PCI_DEVICE_ID_SERVERWORKS_CSB6) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
|
|
PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
|
|
PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
|
|
{ 0, }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE (pci, piix4_ids);
|
|
|
|
static struct i2c_adapter *piix4_main_adapter;
|
|
static struct i2c_adapter *piix4_aux_adapter;
|
|
|
|
static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
|
|
struct i2c_adapter **padap)
|
|
{
|
|
struct i2c_adapter *adap;
|
|
struct i2c_piix4_adapdata *adapdata;
|
|
int retval;
|
|
|
|
adap = kzalloc(sizeof(*adap), GFP_KERNEL);
|
|
if (adap == NULL) {
|
|
release_region(smba, SMBIOSIZE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
adap->owner = THIS_MODULE;
|
|
adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
|
adap->algo = &smbus_algorithm;
|
|
|
|
adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
|
|
if (adapdata == NULL) {
|
|
kfree(adap);
|
|
release_region(smba, SMBIOSIZE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
adapdata->smba = smba;
|
|
|
|
/* set up the sysfs linkage to our parent device */
|
|
adap->dev.parent = &dev->dev;
|
|
|
|
snprintf(adap->name, sizeof(adap->name),
|
|
"SMBus PIIX4 adapter at %04x", smba);
|
|
|
|
i2c_set_adapdata(adap, adapdata);
|
|
|
|
retval = i2c_add_adapter(adap);
|
|
if (retval) {
|
|
dev_err(&dev->dev, "Couldn't register adapter!\n");
|
|
kfree(adapdata);
|
|
kfree(adap);
|
|
release_region(smba, SMBIOSIZE);
|
|
return retval;
|
|
}
|
|
|
|
*padap = adap;
|
|
return 0;
|
|
}
|
|
|
|
static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
int retval;
|
|
|
|
if ((dev->vendor == PCI_VENDOR_ID_ATI &&
|
|
dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
|
|
dev->revision >= 0x40) ||
|
|
dev->vendor == PCI_VENDOR_ID_AMD)
|
|
/* base address location etc changed in SB800 */
|
|
retval = piix4_setup_sb800(dev, id, 0);
|
|
else
|
|
retval = piix4_setup(dev, id);
|
|
|
|
/* If no main SMBus found, give up */
|
|
if (retval < 0)
|
|
return retval;
|
|
|
|
/* Try to register main SMBus adapter, give up if we can't */
|
|
retval = piix4_add_adapter(dev, retval, &piix4_main_adapter);
|
|
if (retval < 0)
|
|
return retval;
|
|
|
|
/* Check for auxiliary SMBus on some AMD chipsets */
|
|
retval = -ENODEV;
|
|
|
|
if (dev->vendor == PCI_VENDOR_ID_ATI &&
|
|
dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
|
|
if (dev->revision < 0x40) {
|
|
retval = piix4_setup_aux(dev, id, 0x58);
|
|
} else {
|
|
/* SB800 added aux bus too */
|
|
retval = piix4_setup_sb800(dev, id, 1);
|
|
}
|
|
}
|
|
|
|
if (dev->vendor == PCI_VENDOR_ID_AMD &&
|
|
dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) {
|
|
retval = piix4_setup_sb800(dev, id, 1);
|
|
}
|
|
|
|
if (retval > 0) {
|
|
/* Try to add the aux adapter if it exists,
|
|
* piix4_add_adapter will clean up if this fails */
|
|
piix4_add_adapter(dev, retval, &piix4_aux_adapter);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void piix4_adap_remove(struct i2c_adapter *adap)
|
|
{
|
|
struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
|
|
|
|
if (adapdata->smba) {
|
|
i2c_del_adapter(adap);
|
|
release_region(adapdata->smba, SMBIOSIZE);
|
|
kfree(adapdata);
|
|
kfree(adap);
|
|
}
|
|
}
|
|
|
|
static void piix4_remove(struct pci_dev *dev)
|
|
{
|
|
if (piix4_main_adapter) {
|
|
piix4_adap_remove(piix4_main_adapter);
|
|
piix4_main_adapter = NULL;
|
|
}
|
|
|
|
if (piix4_aux_adapter) {
|
|
piix4_adap_remove(piix4_aux_adapter);
|
|
piix4_aux_adapter = NULL;
|
|
}
|
|
}
|
|
|
|
static struct pci_driver piix4_driver = {
|
|
.name = "piix4_smbus",
|
|
.id_table = piix4_ids,
|
|
.probe = piix4_probe,
|
|
.remove = piix4_remove,
|
|
};
|
|
|
|
module_pci_driver(piix4_driver);
|
|
|
|
MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
|
|
"Philip Edelbrock <phil@netroedge.com>");
|
|
MODULE_DESCRIPTION("PIIX4 SMBus driver");
|
|
MODULE_LICENSE("GPL");
|