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Pull i2c updates from Wolfram Sang: - New drivers: UniPhier (with and without FIFO) - some drivers got some bigger rework: ismt, designware, img-scb (rcar had to be reverted because issues were showing up just lately) - ACPI: reworked the device scanning and added support for muxes ... and quite a lot of driver bugfixes and cleanups this time. All files touched outside of the i2c realm have proper acks. * 'i2c/for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (70 commits) i2c: rcar: Revert the latest refactoring series i2c: pnx: remove superfluous assignment MAINTAINERS: i2c: drop i2c-pnx maintainer MAINTAINERS: i2c: mark also subdirectories as maintained i2c: cadence: enable driver for ARM64 i2c: i801: Document Intel DNV and Broxton i2c: at91: manage unexpected RXRDY flag when starting a transfer i2c: pnx: Use setup_timer instead of open coding it i2c: add ACPI support for I2C mux ports acpi: add acpi_preset_companion() stub i2c: pxa: Add support for pxa910/988 & new configuration features i2c: au1550: Convert to devm_kzalloc and devm_ioremap_resource i2c-dev: Fix I2C_SLAVE ioctl comment i2c-dev: Fix typo in ioctl name reference i2c: sirf: tune the divider to make i2c bus freq more accurate i2c: imx: Use -ENXIO as error in the NACK case i2c: i801: Add support for Intel Broxton i2c: i801: Add support for Intel DNV i2c: mediatek: add i2c resume support i2c: imx: implement bus recovery ...
727 lines
17 KiB
C
727 lines
17 KiB
C
/*
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* Driver for the Renesas RCar I2C unit
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*
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* Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
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*
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* Copyright (C) 2012-14 Renesas Solutions Corp.
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This file is based on the drivers/i2c/busses/i2c-sh7760.c
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* (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
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*
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* This file used out-of-tree driver i2c-rcar.c
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* Copyright (C) 2011-2012 Renesas Electronics Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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/* register offsets */
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#define ICSCR 0x00 /* slave ctrl */
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#define ICMCR 0x04 /* master ctrl */
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#define ICSSR 0x08 /* slave status */
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#define ICMSR 0x0C /* master status */
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#define ICSIER 0x10 /* slave irq enable */
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#define ICMIER 0x14 /* master irq enable */
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#define ICCCR 0x18 /* clock dividers */
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#define ICSAR 0x1C /* slave address */
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#define ICMAR 0x20 /* master address */
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#define ICRXTX 0x24 /* data port */
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/* ICSCR */
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#define SDBS (1 << 3) /* slave data buffer select */
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#define SIE (1 << 2) /* slave interface enable */
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#define GCAE (1 << 1) /* general call address enable */
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#define FNA (1 << 0) /* forced non acknowledgment */
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/* ICMCR */
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#define MDBS (1 << 7) /* non-fifo mode switch */
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#define FSCL (1 << 6) /* override SCL pin */
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#define FSDA (1 << 5) /* override SDA pin */
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#define OBPC (1 << 4) /* override pins */
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#define MIE (1 << 3) /* master if enable */
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#define TSBE (1 << 2)
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#define FSB (1 << 1) /* force stop bit */
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#define ESG (1 << 0) /* en startbit gen */
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/* ICSSR (also for ICSIER) */
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#define GCAR (1 << 6) /* general call received */
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#define STM (1 << 5) /* slave transmit mode */
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#define SSR (1 << 4) /* stop received */
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#define SDE (1 << 3) /* slave data empty */
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#define SDT (1 << 2) /* slave data transmitted */
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#define SDR (1 << 1) /* slave data received */
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#define SAR (1 << 0) /* slave addr received */
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/* ICMSR (also for ICMIE) */
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#define MNR (1 << 6) /* nack received */
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#define MAL (1 << 5) /* arbitration lost */
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#define MST (1 << 4) /* sent a stop */
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#define MDE (1 << 3)
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#define MDT (1 << 2)
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#define MDR (1 << 1)
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#define MAT (1 << 0) /* slave addr xfer done */
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#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
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#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
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#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
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#define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
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#define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
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#define RCAR_IRQ_STOP (MST)
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#define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF)
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#define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF)
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#define ID_LAST_MSG (1 << 0)
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#define ID_IOERROR (1 << 1)
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#define ID_DONE (1 << 2)
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#define ID_ARBLOST (1 << 3)
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#define ID_NACK (1 << 4)
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enum rcar_i2c_type {
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I2C_RCAR_GEN1,
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I2C_RCAR_GEN2,
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I2C_RCAR_GEN3,
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};
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struct rcar_i2c_priv {
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void __iomem *io;
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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struct clk *clk;
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spinlock_t lock;
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wait_queue_head_t wait;
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int pos;
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u32 icccr;
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u32 flags;
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enum rcar_i2c_type devtype;
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struct i2c_client *slave;
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};
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#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
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#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
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#define rcar_i2c_flags_set(p, f) ((p)->flags |= (f))
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#define rcar_i2c_flags_has(p, f) ((p)->flags & (f))
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#define LOOP_TIMEOUT 1024
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static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
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{
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writel(val, priv->io + reg);
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}
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static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
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{
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return readl(priv->io + reg);
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}
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static void rcar_i2c_init(struct rcar_i2c_priv *priv)
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{
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/* reset master mode */
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rcar_i2c_write(priv, ICMIER, 0);
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rcar_i2c_write(priv, ICMCR, 0);
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rcar_i2c_write(priv, ICMSR, 0);
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rcar_i2c_write(priv, ICMAR, 0);
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}
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static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
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{
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int i;
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for (i = 0; i < LOOP_TIMEOUT; i++) {
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/* make sure that bus is not busy */
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if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
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return 0;
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udelay(1);
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}
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return -EBUSY;
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}
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static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
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u32 bus_speed,
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struct device *dev)
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{
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u32 scgd, cdf;
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u32 round, ick;
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u32 scl;
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u32 cdf_width;
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unsigned long rate;
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switch (priv->devtype) {
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case I2C_RCAR_GEN1:
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cdf_width = 2;
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break;
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case I2C_RCAR_GEN2:
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case I2C_RCAR_GEN3:
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cdf_width = 3;
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break;
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default:
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dev_err(dev, "device type error\n");
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return -EIO;
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}
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/*
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* calculate SCL clock
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* see
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* ICCCR
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*
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* ick = clkp / (1 + CDF)
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* ick : I2C internal clock < 20 MHz
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* ticf : I2C SCL falling time = 35 ns here
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* tr : I2C SCL rising time = 200 ns here
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* intd : LSI internal delay = 50 ns here
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* clkp : peripheral_clk
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* F[] : integer up-valuation
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*/
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rate = clk_get_rate(priv->clk);
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cdf = rate / 20000000;
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if (cdf >= 1U << cdf_width) {
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dev_err(dev, "Input clock %lu too high\n", rate);
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return -EIO;
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}
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ick = rate / (cdf + 1);
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/*
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* it is impossible to calculate large scale
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* number on u32. separate it
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*
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* F[(ticf + tr + intd) * ick]
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* = F[(35 + 200 + 50)ns * ick]
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* = F[285 * ick / 1000000000]
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* = F[(ick / 1000000) * 285 / 1000]
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*/
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round = (ick + 500000) / 1000000 * 285;
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round = (round + 500) / 1000;
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/*
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* Calculation result (= SCL) should be less than
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* bus_speed for hardware safety
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*
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* We could use something along the lines of
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* div = ick / (bus_speed + 1) + 1;
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* scgd = (div - 20 - round + 7) / 8;
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* scl = ick / (20 + (scgd * 8) + round);
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* (not fully verified) but that would get pretty involved
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*/
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for (scgd = 0; scgd < 0x40; scgd++) {
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scl = ick / (20 + (scgd * 8) + round);
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if (scl <= bus_speed)
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goto scgd_find;
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}
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dev_err(dev, "it is impossible to calculate best SCL\n");
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return -EIO;
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scgd_find:
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dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
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scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
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/*
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* keep icccr value
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*/
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priv->icccr = scgd << cdf_width | cdf;
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return 0;
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}
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static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
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{
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int read = !!rcar_i2c_is_recv(priv);
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rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
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rcar_i2c_write(priv, ICMSR, 0);
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
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rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
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}
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/*
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* interrupt functions
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*/
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static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
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{
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struct i2c_msg *msg = priv->msg;
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/*
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* FIXME
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* sometimes, unknown interrupt happened.
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* Do nothing
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*/
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if (!(msr & MDE))
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return 0;
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/*
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* If address transfer phase finished,
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* goto data phase.
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*/
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if (msr & MAT)
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
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if (priv->pos < msg->len) {
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/*
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* Prepare next data to ICRXTX register.
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* This data will go to _SHIFT_ register.
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*
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* *
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* [ICRXTX] -> [SHIFT] -> [I2C bus]
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*/
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rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
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priv->pos++;
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} else {
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/*
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* The last data was pushed to ICRXTX on _PREV_ empty irq.
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* It is on _SHIFT_ register, and will sent to I2C bus.
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*
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* *
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* [ICRXTX] -> [SHIFT] -> [I2C bus]
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*/
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if (priv->flags & ID_LAST_MSG)
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/*
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* If current msg is the _LAST_ msg,
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* prepare stop condition here.
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* ID_DONE will be set on STOP irq.
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*/
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
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else
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/*
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* If current msg is _NOT_ last msg,
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* it doesn't call stop phase.
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* thus, there is no STOP irq.
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* return ID_DONE here.
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*/
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return ID_DONE;
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}
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rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
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return 0;
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}
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static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
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{
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struct i2c_msg *msg = priv->msg;
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/*
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* FIXME
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* sometimes, unknown interrupt happened.
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* Do nothing
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*/
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if (!(msr & MDR))
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return 0;
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if (msr & MAT) {
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/*
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* Address transfer phase finished,
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* but, there is no data at this point.
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* Do nothing.
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*/
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} else if (priv->pos < msg->len) {
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/*
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* get received data
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*/
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msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
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priv->pos++;
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}
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/*
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* If next received data is the _LAST_,
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* go to STOP phase,
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* otherwise, go to DATA phase.
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*/
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if (priv->pos + 1 >= msg->len)
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
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else
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
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rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
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return 0;
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}
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static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
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{
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u32 ssr_raw, ssr_filtered;
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u8 value;
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ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
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ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
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if (!ssr_filtered)
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return false;
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/* address detected */
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if (ssr_filtered & SAR) {
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/* read or write request */
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if (ssr_raw & STM) {
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i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
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rcar_i2c_write(priv, ICRXTX, value);
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rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
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} else {
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i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
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rcar_i2c_read(priv, ICRXTX); /* dummy read */
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rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
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}
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rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
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}
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/* master sent stop */
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if (ssr_filtered & SSR) {
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i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
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rcar_i2c_write(priv, ICSIER, SAR | SSR);
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rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
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}
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/* master wants to write to us */
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if (ssr_filtered & SDR) {
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int ret;
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value = rcar_i2c_read(priv, ICRXTX);
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ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
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/* Send NACK in case of error */
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rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
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rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
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}
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/* master wants to read from us */
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if (ssr_filtered & SDE) {
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i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
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rcar_i2c_write(priv, ICRXTX, value);
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rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
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}
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return true;
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}
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static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
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{
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struct rcar_i2c_priv *priv = ptr;
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irqreturn_t result = IRQ_HANDLED;
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u32 msr;
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/*-------------- spin lock -----------------*/
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spin_lock(&priv->lock);
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if (rcar_i2c_slave_irq(priv))
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goto exit;
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msr = rcar_i2c_read(priv, ICMSR);
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/* Only handle interrupts that are currently enabled */
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msr &= rcar_i2c_read(priv, ICMIER);
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if (!msr) {
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result = IRQ_NONE;
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goto exit;
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}
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/* Arbitration lost */
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if (msr & MAL) {
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rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
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goto out;
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}
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/* Nack */
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if (msr & MNR) {
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/* go to stop phase */
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rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
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rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
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rcar_i2c_flags_set(priv, ID_NACK);
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goto out;
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}
|
|
|
|
/* Stop */
|
|
if (msr & MST) {
|
|
rcar_i2c_flags_set(priv, ID_DONE);
|
|
goto out;
|
|
}
|
|
|
|
if (rcar_i2c_is_recv(priv))
|
|
rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
|
|
else
|
|
rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
|
|
|
|
out:
|
|
if (rcar_i2c_flags_has(priv, ID_DONE)) {
|
|
rcar_i2c_write(priv, ICMIER, 0);
|
|
rcar_i2c_write(priv, ICMSR, 0);
|
|
wake_up(&priv->wait);
|
|
}
|
|
|
|
exit:
|
|
spin_unlock(&priv->lock);
|
|
/*-------------- spin unlock -----------------*/
|
|
|
|
return result;
|
|
}
|
|
|
|
static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
|
|
struct i2c_msg *msgs,
|
|
int num)
|
|
{
|
|
struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
|
|
struct device *dev = rcar_i2c_priv_to_dev(priv);
|
|
unsigned long flags;
|
|
int i, ret;
|
|
long timeout;
|
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
/*-------------- spin lock -----------------*/
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
rcar_i2c_init(priv);
|
|
/* start clock */
|
|
rcar_i2c_write(priv, ICCCR, priv->icccr);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
/*-------------- spin unlock -----------------*/
|
|
|
|
ret = rcar_i2c_bus_barrier(priv);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
/* This HW can't send STOP after address phase */
|
|
if (msgs[i].len == 0) {
|
|
ret = -EOPNOTSUPP;
|
|
break;
|
|
}
|
|
|
|
/*-------------- spin lock -----------------*/
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
/* init each data */
|
|
priv->msg = &msgs[i];
|
|
priv->pos = 0;
|
|
priv->flags = 0;
|
|
if (i == num - 1)
|
|
rcar_i2c_flags_set(priv, ID_LAST_MSG);
|
|
|
|
rcar_i2c_prepare_msg(priv);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
/*-------------- spin unlock -----------------*/
|
|
|
|
timeout = wait_event_timeout(priv->wait,
|
|
rcar_i2c_flags_has(priv, ID_DONE),
|
|
adap->timeout);
|
|
if (!timeout) {
|
|
ret = -ETIMEDOUT;
|
|
break;
|
|
}
|
|
|
|
if (rcar_i2c_flags_has(priv, ID_NACK)) {
|
|
ret = -ENXIO;
|
|
break;
|
|
}
|
|
|
|
if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
|
|
ret = -EAGAIN;
|
|
break;
|
|
}
|
|
|
|
if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
|
|
ret = -EIO;
|
|
break;
|
|
}
|
|
|
|
ret = i + 1; /* The number of transfer */
|
|
}
|
|
out:
|
|
pm_runtime_put(dev);
|
|
|
|
if (ret < 0 && ret != -ENXIO)
|
|
dev_err(dev, "error %d : %x\n", ret, priv->flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rcar_reg_slave(struct i2c_client *slave)
|
|
{
|
|
struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
|
|
|
|
if (priv->slave)
|
|
return -EBUSY;
|
|
|
|
if (slave->flags & I2C_CLIENT_TEN)
|
|
return -EAFNOSUPPORT;
|
|
|
|
pm_runtime_forbid(rcar_i2c_priv_to_dev(priv));
|
|
|
|
priv->slave = slave;
|
|
rcar_i2c_write(priv, ICSAR, slave->addr);
|
|
rcar_i2c_write(priv, ICSSR, 0);
|
|
rcar_i2c_write(priv, ICSIER, SAR | SSR);
|
|
rcar_i2c_write(priv, ICSCR, SIE | SDBS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rcar_unreg_slave(struct i2c_client *slave)
|
|
{
|
|
struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
|
|
|
|
WARN_ON(!priv->slave);
|
|
|
|
rcar_i2c_write(priv, ICSIER, 0);
|
|
rcar_i2c_write(priv, ICSCR, 0);
|
|
|
|
priv->slave = NULL;
|
|
|
|
pm_runtime_allow(rcar_i2c_priv_to_dev(priv));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u32 rcar_i2c_func(struct i2c_adapter *adap)
|
|
{
|
|
/* This HW can't do SMBUS_QUICK and NOSTART */
|
|
return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
|
|
(I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
|
|
}
|
|
|
|
static const struct i2c_algorithm rcar_i2c_algo = {
|
|
.master_xfer = rcar_i2c_master_xfer,
|
|
.functionality = rcar_i2c_func,
|
|
.reg_slave = rcar_reg_slave,
|
|
.unreg_slave = rcar_unreg_slave,
|
|
};
|
|
|
|
static const struct of_device_id rcar_i2c_dt_ids[] = {
|
|
{ .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
|
|
{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
|
|
{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
|
|
{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
|
|
{ .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
|
|
|
|
static int rcar_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
struct rcar_i2c_priv *priv;
|
|
struct i2c_adapter *adap;
|
|
struct resource *res;
|
|
struct device *dev = &pdev->dev;
|
|
u32 bus_speed;
|
|
int irq, ret;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(priv->clk)) {
|
|
dev_err(dev, "cannot get clock\n");
|
|
return PTR_ERR(priv->clk);
|
|
}
|
|
|
|
bus_speed = 100000; /* default 100 kHz */
|
|
of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
|
|
|
|
priv->devtype = (enum rcar_i2c_type)of_match_device(rcar_i2c_dt_ids, dev)->data;
|
|
|
|
ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
priv->io = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(priv->io))
|
|
return PTR_ERR(priv->io);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
init_waitqueue_head(&priv->wait);
|
|
spin_lock_init(&priv->lock);
|
|
|
|
adap = &priv->adap;
|
|
adap->nr = pdev->id;
|
|
adap->algo = &rcar_i2c_algo;
|
|
adap->class = I2C_CLASS_DEPRECATED;
|
|
adap->retries = 3;
|
|
adap->dev.parent = dev;
|
|
adap->dev.of_node = dev->of_node;
|
|
i2c_set_adapdata(adap, priv);
|
|
strlcpy(adap->name, pdev->name, sizeof(adap->name));
|
|
|
|
ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
|
|
dev_name(dev), priv);
|
|
if (ret < 0) {
|
|
dev_err(dev, "cannot get irq %d\n", irq);
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
ret = i2c_add_numbered_adapter(adap);
|
|
if (ret < 0) {
|
|
dev_err(dev, "reg adap failed: %d\n", ret);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
dev_info(dev, "probed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rcar_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
|
|
struct device *dev = &pdev->dev;
|
|
|
|
i2c_del_adapter(&priv->adap);
|
|
pm_runtime_disable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver rcar_i2c_driver = {
|
|
.driver = {
|
|
.name = "i2c-rcar",
|
|
.of_match_table = rcar_i2c_dt_ids,
|
|
},
|
|
.probe = rcar_i2c_probe,
|
|
.remove = rcar_i2c_remove,
|
|
};
|
|
|
|
module_platform_driver(rcar_i2c_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
|
|
MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
|