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![Uwe Kleine-König](/assets/img/avatar_default.png)
imx1_pinconf_set assumes that the array of pins in struct imx1_pinctrl_soc_info can be indexed by pin id to get the pinctrl_pin_desc for a pin. This used to be correct up to commit607af165c0
which removed some entries from the array and so made it wrong to access the array by pin id. The result of this bug is a wrong pin name in the output for small pin ids and an oops for the bigger ones. This patch is the result of a discussion that includes patches by Markus Pargmann and Chris Ruehl. Fixes:607af165c0
("pinctrl: i.MX27: Remove nonexistent pad definitions") Cc: stable@vger.kernel.org Reported-by: Chris Ruehl <chris.ruehl@gtsys.com.hk> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
659 lines
17 KiB
C
659 lines
17 KiB
C
/*
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* Core driver for the imx pin controller in imx1/21/27
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*
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* Copyright (C) 2013 Pengutronix
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* Author: Markus Pargmann <mpa@pengutronix.de>
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*
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* Based on pinctrl-imx.c:
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* Author: Dong Aisheng <dong.aisheng@linaro.org>
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Copyright (C) 2012 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/slab.h>
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#include "../core.h"
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#include "pinctrl-imx1.h"
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struct imx1_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pctl;
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void __iomem *base;
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const struct imx1_pinctrl_soc_info *info;
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};
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/*
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* MX1 register offsets
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*/
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#define MX1_DDIR 0x00
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#define MX1_OCR 0x04
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#define MX1_ICONFA 0x0c
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#define MX1_ICONFB 0x14
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#define MX1_GIUS 0x20
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#define MX1_GPR 0x38
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#define MX1_PUEN 0x40
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#define MX1_PORT_STRIDE 0x100
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/*
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* MUX_ID format defines
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*/
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#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
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#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
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#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
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#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
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#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
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#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
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/*
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* IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
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* control register are seperated into function, output configuration, input
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* configuration A, input configuration B, GPIO in use and data direction.
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*
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* Those controls that are represented by 1 bit have a direct mapping between
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* bit position and pin id. If they are represented by 2 bit, the lower 16 pins
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* are in the first register and the upper 16 pins in the second (next)
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* register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
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*/
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/*
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* Calculates the register offset from a pin_id
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*/
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static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
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{
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unsigned int port = pin_id / 32;
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return ipctl->base + port * MX1_PORT_STRIDE;
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}
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/*
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* Write to a register with 2 bits per pin. The function will automatically
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* use the next register if the pin is managed in the second register.
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*/
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static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
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u32 value, u32 reg_offset)
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{
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void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
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int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
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int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
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u32 old_val;
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u32 new_val;
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/* Use the next register if the pin's port pin number is >=16 */
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if (pin_id % 32 >= 16)
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reg += 0x04;
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dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
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reg, offset, value);
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/* Get current state of pins */
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old_val = readl(reg);
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old_val &= mask;
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new_val = value & 0x3; /* Make sure value is really 2 bit */
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new_val <<= offset;
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new_val |= old_val;/* Set new state for pin_id */
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writel(new_val, reg);
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}
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static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
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u32 value, u32 reg_offset)
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{
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void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
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int offset = pin_id % 32;
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int mask = ~BIT_MASK(offset);
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u32 old_val;
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u32 new_val;
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/* Get current state of pins */
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old_val = readl(reg);
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old_val &= mask;
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new_val = value & 0x1; /* Make sure value is really 1 bit */
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new_val <<= offset;
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new_val |= old_val;/* Set new state for pin_id */
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writel(new_val, reg);
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}
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static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
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u32 reg_offset)
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{
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void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
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int offset = (pin_id % 16) * 2;
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/* Use the next register if the pin's port pin number is >=16 */
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if (pin_id % 32 >= 16)
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reg += 0x04;
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return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
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}
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static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
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u32 reg_offset)
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{
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void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
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int offset = pin_id % 32;
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return !!(readl(reg) & BIT(offset));
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}
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static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
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const struct imx1_pinctrl_soc_info *info,
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const char *name)
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{
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const struct imx1_pin_group *grp = NULL;
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int i;
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for (i = 0; i < info->ngroups; i++) {
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if (!strcmp(info->groups[i].name, name)) {
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grp = &info->groups[i];
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break;
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}
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}
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return grp;
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}
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static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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return info->ngroups;
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}
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static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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return info->groups[selector].name;
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}
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static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
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const unsigned int **pins,
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unsigned *npins)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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if (selector >= info->ngroups)
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return -EINVAL;
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*pins = info->groups[selector].pin_ids;
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*npins = info->groups[selector].npins;
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return 0;
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}
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static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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unsigned offset)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
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imx1_read_bit(ipctl, offset, MX1_GIUS),
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imx1_read_bit(ipctl, offset, MX1_GPR),
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imx1_read_bit(ipctl, offset, MX1_DDIR),
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imx1_read_2bit(ipctl, offset, MX1_OCR),
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imx1_read_2bit(ipctl, offset, MX1_ICONFA),
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imx1_read_2bit(ipctl, offset, MX1_ICONFB));
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}
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static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *np,
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struct pinctrl_map **map, unsigned *num_maps)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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const struct imx1_pin_group *grp;
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struct pinctrl_map *new_map;
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struct device_node *parent;
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int map_num = 1;
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int i, j;
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/*
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* first find the group of this node and check if we need create
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* config maps for pins
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*/
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grp = imx1_pinctrl_find_group_by_name(info, np->name);
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if (!grp) {
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dev_err(info->dev, "unable to find group for node %s\n",
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np->name);
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return -EINVAL;
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}
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for (i = 0; i < grp->npins; i++)
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map_num++;
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new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
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if (!new_map)
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return -ENOMEM;
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*map = new_map;
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*num_maps = map_num;
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/* create mux map */
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parent = of_get_parent(np);
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if (!parent) {
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kfree(new_map);
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return -EINVAL;
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}
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new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
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new_map[0].data.mux.function = parent->name;
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new_map[0].data.mux.group = np->name;
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of_node_put(parent);
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/* create config map */
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new_map++;
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for (i = j = 0; i < grp->npins; i++) {
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new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
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new_map[j].data.configs.group_or_pin =
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pin_get_name(pctldev, grp->pins[i].pin_id);
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new_map[j].data.configs.configs = &grp->pins[i].config;
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new_map[j].data.configs.num_configs = 1;
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j++;
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}
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dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
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(*map)->data.mux.function, (*map)->data.mux.group, map_num);
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return 0;
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}
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static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map, unsigned num_maps)
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{
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kfree(map);
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}
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static const struct pinctrl_ops imx1_pctrl_ops = {
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.get_groups_count = imx1_get_groups_count,
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.get_group_name = imx1_get_group_name,
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.get_group_pins = imx1_get_group_pins,
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.pin_dbg_show = imx1_pin_dbg_show,
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.dt_node_to_map = imx1_dt_node_to_map,
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.dt_free_map = imx1_dt_free_map,
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};
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static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
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unsigned group)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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const struct imx1_pin *pins;
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unsigned int npins;
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int i;
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/*
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* Configure the mux mode for each pin in the group for a specific
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* function.
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*/
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pins = info->groups[group].pins;
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npins = info->groups[group].npins;
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WARN_ON(!pins || !npins);
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dev_dbg(ipctl->dev, "enable function %s group %s\n",
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info->functions[selector].name, info->groups[group].name);
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for (i = 0; i < npins; i++) {
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unsigned int mux = pins[i].mux_id;
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unsigned int pin_id = pins[i].pin_id;
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unsigned int afunction = MX1_MUX_FUNCTION(mux);
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unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
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unsigned int direction = MX1_MUX_DIR(mux);
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unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
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unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
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unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
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dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
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__func__, pin_id, afunction, gpio_in_use,
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direction, gpio_oconf, gpio_iconfa,
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gpio_iconfb);
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imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
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imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
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if (gpio_in_use) {
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imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
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imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
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MX1_ICONFA);
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imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
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MX1_ICONFB);
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} else {
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imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
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}
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}
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return 0;
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}
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static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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return info->nfunctions;
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}
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static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
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unsigned selector)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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return info->functions[selector].name;
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}
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static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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*groups = info->functions[selector].groups;
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*num_groups = info->functions[selector].num_groups;
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return 0;
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}
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static const struct pinmux_ops imx1_pmx_ops = {
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.get_functions_count = imx1_pmx_get_funcs_count,
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.get_function_name = imx1_pmx_get_func_name,
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.get_function_groups = imx1_pmx_get_groups,
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.set_mux = imx1_pmx_set,
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};
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static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned pin_id, unsigned long *config)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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*config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
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return 0;
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}
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static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
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unsigned pin_id, unsigned long *configs,
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unsigned num_configs)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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int i;
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for (i = 0; i != num_configs; ++i) {
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imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
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dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
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pin_desc_get(pctldev, pin_id)->name);
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}
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return 0;
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}
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static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned pin_id)
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{
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unsigned long config;
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imx1_pinconf_get(pctldev, pin_id, &config);
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seq_printf(s, "0x%lx", config);
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}
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static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned group)
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{
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struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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const struct imx1_pinctrl_soc_info *info = ipctl->info;
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struct imx1_pin_group *grp;
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unsigned long config;
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const char *name;
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int i, ret;
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if (group > info->ngroups)
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return;
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seq_puts(s, "\n");
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grp = &info->groups[group];
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for (i = 0; i < grp->npins; i++) {
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name = pin_get_name(pctldev, grp->pins[i].pin_id);
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ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
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if (ret)
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return;
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seq_printf(s, "%s: 0x%lx", name, config);
|
|
}
|
|
}
|
|
|
|
static const struct pinconf_ops imx1_pinconf_ops = {
|
|
.pin_config_get = imx1_pinconf_get,
|
|
.pin_config_set = imx1_pinconf_set,
|
|
.pin_config_dbg_show = imx1_pinconf_dbg_show,
|
|
.pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
|
|
};
|
|
|
|
static struct pinctrl_desc imx1_pinctrl_desc = {
|
|
.pctlops = &imx1_pctrl_ops,
|
|
.pmxops = &imx1_pmx_ops,
|
|
.confops = &imx1_pinconf_ops,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int imx1_pinctrl_parse_groups(struct device_node *np,
|
|
struct imx1_pin_group *grp,
|
|
struct imx1_pinctrl_soc_info *info,
|
|
u32 index)
|
|
{
|
|
int size;
|
|
const __be32 *list;
|
|
int i;
|
|
|
|
dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
|
|
|
|
/* Initialise group */
|
|
grp->name = np->name;
|
|
|
|
/*
|
|
* the binding format is fsl,pins = <PIN MUX_ID CONFIG>
|
|
*/
|
|
list = of_get_property(np, "fsl,pins", &size);
|
|
/* we do not check return since it's safe node passed down */
|
|
if (!size || size % 12) {
|
|
dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
|
|
np->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
grp->npins = size / 12;
|
|
grp->pins = devm_kzalloc(info->dev,
|
|
grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
|
|
grp->pin_ids = devm_kzalloc(info->dev,
|
|
grp->npins * sizeof(unsigned int), GFP_KERNEL);
|
|
|
|
if (!grp->pins || !grp->pin_ids)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < grp->npins; i++) {
|
|
grp->pins[i].pin_id = be32_to_cpu(*list++);
|
|
grp->pins[i].mux_id = be32_to_cpu(*list++);
|
|
grp->pins[i].config = be32_to_cpu(*list++);
|
|
|
|
grp->pin_ids[i] = grp->pins[i].pin_id;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int imx1_pinctrl_parse_functions(struct device_node *np,
|
|
struct imx1_pinctrl_soc_info *info,
|
|
u32 index)
|
|
{
|
|
struct device_node *child;
|
|
struct imx1_pmx_func *func;
|
|
struct imx1_pin_group *grp;
|
|
int ret;
|
|
static u32 grp_index;
|
|
u32 i = 0;
|
|
|
|
dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
|
|
|
|
func = &info->functions[index];
|
|
|
|
/* Initialise function */
|
|
func->name = np->name;
|
|
func->num_groups = of_get_child_count(np);
|
|
if (func->num_groups == 0)
|
|
return -EINVAL;
|
|
|
|
func->groups = devm_kzalloc(info->dev,
|
|
func->num_groups * sizeof(char *), GFP_KERNEL);
|
|
|
|
if (!func->groups)
|
|
return -ENOMEM;
|
|
|
|
for_each_child_of_node(np, child) {
|
|
func->groups[i] = child->name;
|
|
grp = &info->groups[grp_index++];
|
|
ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
|
|
if (ret == -ENOMEM)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
|
|
struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct device_node *child;
|
|
int ret;
|
|
u32 nfuncs = 0;
|
|
u32 ngroups = 0;
|
|
u32 ifunc = 0;
|
|
|
|
if (!np)
|
|
return -ENODEV;
|
|
|
|
for_each_child_of_node(np, child) {
|
|
++nfuncs;
|
|
ngroups += of_get_child_count(child);
|
|
}
|
|
|
|
if (!nfuncs) {
|
|
dev_err(&pdev->dev, "No pin functions defined\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
info->nfunctions = nfuncs;
|
|
info->functions = devm_kzalloc(&pdev->dev,
|
|
nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
|
|
|
|
info->ngroups = ngroups;
|
|
info->groups = devm_kzalloc(&pdev->dev,
|
|
ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
|
|
|
|
|
|
if (!info->functions || !info->groups)
|
|
return -ENOMEM;
|
|
|
|
for_each_child_of_node(np, child) {
|
|
ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
|
|
if (ret == -ENOMEM)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int imx1_pinctrl_core_probe(struct platform_device *pdev,
|
|
struct imx1_pinctrl_soc_info *info)
|
|
{
|
|
struct imx1_pinctrl *ipctl;
|
|
struct resource *res;
|
|
struct pinctrl_desc *pctl_desc;
|
|
int ret;
|
|
|
|
if (!info || !info->pins || !info->npins) {
|
|
dev_err(&pdev->dev, "wrong pinctrl info\n");
|
|
return -EINVAL;
|
|
}
|
|
info->dev = &pdev->dev;
|
|
|
|
/* Create state holders etc for this driver */
|
|
ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
|
|
if (!ipctl)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENOENT;
|
|
|
|
ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
|
|
resource_size(res));
|
|
if (!ipctl->base)
|
|
return -ENOMEM;
|
|
|
|
pctl_desc = &imx1_pinctrl_desc;
|
|
pctl_desc->name = dev_name(&pdev->dev);
|
|
pctl_desc->pins = info->pins;
|
|
pctl_desc->npins = info->npins;
|
|
|
|
ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "fail to probe dt properties\n");
|
|
return ret;
|
|
}
|
|
|
|
ipctl->info = info;
|
|
ipctl->dev = info->dev;
|
|
platform_set_drvdata(pdev, ipctl);
|
|
ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
|
|
if (IS_ERR(ipctl->pctl)) {
|
|
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
|
|
return PTR_ERR(ipctl->pctl);
|
|
}
|
|
|
|
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
|
|
if (ret) {
|
|
pinctrl_unregister(ipctl->pctl);
|
|
dev_err(&pdev->dev, "Failed to populate subdevices\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
int imx1_pinctrl_core_remove(struct platform_device *pdev)
|
|
{
|
|
struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev);
|
|
|
|
pinctrl_unregister(ipctl->pctl);
|
|
|
|
return 0;
|
|
}
|