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![Linus Torvalds](/assets/img/avatar_default.png)
- Core functionality: - Enable exclusive pin ownership: it is possible to flag a pin controller so that GPIO and other functions cannot use a single pin simultaneously. - New drivers: - NXP LPC18xx System Control Unit pin controller - Imagination Pistachio SoC pin controller - New subdrivers: - Freescale i.MX7d SoC - Intel Sunrisepoint-H PCH - Renesas PFC R8A7793 - Renesas PFC R8A7794 - Mediatek MT6397, MT8127 - SiRF Atlas 7 - Allwinner A33 - Qualcomm MSM8660 - Marvell Armada 395 - Rockchip RK3368 - Cleanups: - A big cleanup of the Marvell MVEBU driver rectifying it to correspond to reality - Drop platform device probing from the SH PFC driver, we are now a DT only shop for SuperH - Drop obsolte multi-platform check for SH PFC - Various janitorial: constification, grammar etc - Improvements: - The AT91 GPIO portions now supports the set_multiple() feature - Split out SPI pins on the Xilinx Zynq - Support DTs without specific function nodes in the i.MX driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVin37AAoJEEEQszewGV1zIlQP/i6+C47z3OV67hYAOmlGoynl wsdTFbyp+GIPl3N1r0lRzxOfQsuc9t93iDMrC5ssN9VFaj8MgH/j3XKWf5A55iVn u7nNQzIFjzTwl58/Pu4oM+d9l5i26o44teFKh3xI4aup4AFed3+lDkQtRipgo29c V4y+6SaQxQ46e2qaOAM20gEagm2a8EvChn1Zo/HLQnnmZcKBxgObJna7iTZWm+fN LzyBWtczFYPxfQ9IqYzklyeou4ohfrcHzqN71IEtmGMXxob+i04QS9FQXaPitgBG UORjwFVh8690n3ETQobjLrylOF5F/3+RdCGqanYOLgaJ0aix4+EByLz9FbxLPnJk 4Utijk2SKxLUb3dXZIfpwKtmPmvLJkFqwSazN5WDIg9Rjqz/H1p9UTWP0cfPRwJa 9INDZeK833kjYdtK6UMBpuNFkgGtpKTlhMX/cI78KYsEwVgK8r69b7uNr+2OUMgh 4i7dbHgb5/NpHlUlacVPTBvXf7C1iQ//vqh0Oc20lp/mAY1tVGuYRHno6QVyRtfS DmCNPtbAgCa9FmP/t5NA8a3wana2ObTT2NCNMGEue7tJxVX4YaLpwIAEnUSHSJOQ seI8HT2M1yEiSes9V+OuigHt3pKk68fMe0ZqDkovcd4QBlub6WTAPXWrXpbHtBCo k+hT8TlDYaDbQkNDzXtg =UyKm -----END PGP SIGNATURE----- Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "Here is the bulk of pin control changes for the v4.2 series: Quite a lot of new SoC subdrivers and two new main drivers this time, apart from that business as usual. Details: Core functionality: - Enable exclusive pin ownership: it is possible to flag a pin controller so that GPIO and other functions cannot use a single pin simultaneously. New drivers: - NXP LPC18xx System Control Unit pin controller - Imagination Pistachio SoC pin controller New subdrivers: - Freescale i.MX7d SoC - Intel Sunrisepoint-H PCH - Renesas PFC R8A7793 - Renesas PFC R8A7794 - Mediatek MT6397, MT8127 - SiRF Atlas 7 - Allwinner A33 - Qualcomm MSM8660 - Marvell Armada 395 - Rockchip RK3368 Cleanups: - A big cleanup of the Marvell MVEBU driver rectifying it to correspond to reality - Drop platform device probing from the SH PFC driver, we are now a DT only shop for SuperH - Drop obsolte multi-platform check for SH PFC - Various janitorial: constification, grammar etc Improvements: - The AT91 GPIO portions now supports the set_multiple() feature - Split out SPI pins on the Xilinx Zynq - Support DTs without specific function nodes in the i.MX driver" * tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: rockchip: add support for the rk3368 pinctrl: rockchip: generalize perpin driver-strength setting pinctrl: sh-pfc: r8a7794: add SDHI pin groups pinctrl: sh-pfc: r8a7794: add MMCIF pin groups pinctrl: sh-pfc: add R8A7794 PFC support pinctrl: make pinctrl_register() return proper error code pinctrl: mvebu: armada-39x: add support for Armada 395 variant pinctrl: mvebu: armada-39x: add missing SATA functions pinctrl: mvebu: armada-39x: add missing PCIe functions pinctrl: mvebu: armada-38x: add ptp functions pinctrl: mvebu: armada-38x: add ua1 functions pinctrl: mvebu: armada-38x: add nand functions pinctrl: mvebu: armada-38x: add sata functions pinctrl: mvebu: armada-xp: add dram functions pinctrl: mvebu: armada-xp: add nand rb function pinctrl: mvebu: armada-xp: add spi1 function pinctrl: mvebu: armada-39x: normalize ref clock naming pinctrl: mvebu: armada-xp: rename spi to spi0 pinctrl: mvebu: armada-370: align spi1 clock pin naming pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet ...
766 lines
20 KiB
C
766 lines
20 KiB
C
/*
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* Pin controller and GPIO driver for Amlogic Meson SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
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* BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
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* X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
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* variable number of pins.
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*
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* The AO bank is special because it belongs to the Always-On power
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* domain which can't be powered off; the bank also uses a set of
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* registers different from the other banks.
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*
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* For each of the two power domains (regular and always-on) there are
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* 4 different register ranges that control the following properties
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* of the pins:
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* 1) pin muxing
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* 2) pull enable/disable
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* 3) pull up/down
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* 4) GPIO direction, output value, input value
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*
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* In some cases the register ranges for pull enable and pull
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* direction are the same and thus there are only 3 register ranges.
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*
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* Every pinmux group can be enabled by a specific bit in the first
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* register range of the domain; when all groups for a given pin are
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* disabled the pin acts as a GPIO.
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*
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* For the pull and GPIO configuration every bank uses a contiguous
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* set of bits in the register sets described above; the same register
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* can be shared by more banks with different offsets.
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*
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* In addition to this there are some registers shared between all
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* banks that control the IRQ functionality. This feature is not
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* supported at the moment by the driver.
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*/
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/seq_file.h>
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#include "../core.h"
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#include "../pinctrl-utils.h"
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#include "pinctrl-meson.h"
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/**
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* meson_get_bank() - find the bank containing a given pin
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*
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* @domain: the domain containing the pin
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* @pin: the pin number
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* @bank: the found bank
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*
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* Return: 0 on success, a negative value on error
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*/
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static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
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struct meson_bank **bank)
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{
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int i;
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for (i = 0; i < domain->data->num_banks; i++) {
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if (pin >= domain->data->banks[i].first &&
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pin <= domain->data->banks[i].last) {
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*bank = &domain->data->banks[i];
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return 0;
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}
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}
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return -EINVAL;
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}
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/**
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* meson_get_domain_and_bank() - find domain and bank containing a given pin
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*
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* @pc: Meson pin controller device
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* @pin: the pin number
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* @domain: the found domain
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* @bank: the found bank
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*
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* Return: 0 on success, a negative value on error
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*/
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static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
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struct meson_domain **domain,
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struct meson_bank **bank)
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{
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struct meson_domain *d;
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int i;
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for (i = 0; i < pc->data->num_domains; i++) {
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d = &pc->domains[i];
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if (pin >= d->data->pin_base &&
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pin < d->data->pin_base + d->data->num_pins) {
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*domain = d;
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return meson_get_bank(d, pin, bank);
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}
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}
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return -EINVAL;
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}
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/**
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* meson_calc_reg_and_bit() - calculate register and bit for a pin
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*
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* @bank: the bank containing the pin
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* @pin: the pin number
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* @reg_type: the type of register needed (pull-enable, pull, etc...)
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* @reg: the computed register offset
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* @bit: the computed bit
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*/
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static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
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enum meson_reg_type reg_type,
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unsigned int *reg, unsigned int *bit)
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{
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struct meson_reg_desc *desc = &bank->regs[reg_type];
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*reg = desc->reg * 4;
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*bit = desc->bit + pin - bank->first;
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}
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static int meson_get_groups_count(struct pinctrl_dev *pcdev)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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return pc->data->num_groups;
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}
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static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
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unsigned selector)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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return pc->data->groups[selector].name;
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}
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static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
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const unsigned **pins, unsigned *num_pins)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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*pins = pc->data->groups[selector].pins;
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*num_pins = pc->data->groups[selector].num_pins;
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return 0;
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}
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static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
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unsigned offset)
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{
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seq_printf(s, " %s", dev_name(pcdev->dev));
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}
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static const struct pinctrl_ops meson_pctrl_ops = {
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.get_groups_count = meson_get_groups_count,
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.get_group_name = meson_get_group_name,
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.get_group_pins = meson_get_group_pins,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
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.dt_free_map = pinctrl_utils_dt_free_map,
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.pin_dbg_show = meson_pin_dbg_show,
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};
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/**
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* meson_pmx_disable_other_groups() - disable other groups using a given pin
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*
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* @pc: meson pin controller device
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* @pin: number of the pin
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* @sel_group: index of the selected group, or -1 if none
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*
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* The function disables all pinmux groups using a pin except the
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* selected one. If @sel_group is -1 all groups are disabled, leaving
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* the pin in GPIO mode.
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*/
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static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
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unsigned int pin, int sel_group)
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{
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struct meson_pmx_group *group;
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struct meson_domain *domain;
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int i, j;
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for (i = 0; i < pc->data->num_groups; i++) {
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group = &pc->data->groups[i];
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if (group->is_gpio || i == sel_group)
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continue;
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for (j = 0; j < group->num_pins; j++) {
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if (group->pins[j] == pin) {
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/* We have found a group using the pin */
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domain = &pc->domains[group->domain];
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regmap_update_bits(domain->reg_mux,
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group->reg * 4,
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BIT(group->bit), 0);
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}
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}
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}
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}
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static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
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unsigned group_num)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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struct meson_pmx_func *func = &pc->data->funcs[func_num];
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struct meson_pmx_group *group = &pc->data->groups[group_num];
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struct meson_domain *domain = &pc->domains[group->domain];
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int i, ret = 0;
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dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
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group->name);
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/*
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* Disable groups using the same pin.
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* The selected group is not disabled to avoid glitches.
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*/
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for (i = 0; i < group->num_pins; i++)
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meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
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/* Function 0 (GPIO) doesn't need any additional setting */
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if (func_num)
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ret = regmap_update_bits(domain->reg_mux, group->reg * 4,
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BIT(group->bit), BIT(group->bit));
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return ret;
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}
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static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
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struct pinctrl_gpio_range *range,
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unsigned offset)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);
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return 0;
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}
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static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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return pc->data->num_funcs;
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}
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static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
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unsigned selector)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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return pc->data->funcs[selector].name;
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}
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static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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*groups = pc->data->funcs[selector].groups;
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*num_groups = pc->data->funcs[selector].num_groups;
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return 0;
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}
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static const struct pinmux_ops meson_pmx_ops = {
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.set_mux = meson_pmx_set_mux,
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.get_functions_count = meson_pmx_get_funcs_count,
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.get_function_name = meson_pmx_get_func_name,
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.get_function_groups = meson_pmx_get_groups,
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.gpio_request_enable = meson_pmx_request_gpio,
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};
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static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
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unsigned long *configs, unsigned num_configs)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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struct meson_domain *domain;
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struct meson_bank *bank;
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enum pin_config_param param;
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unsigned int reg, bit;
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int i, ret;
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u16 arg;
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ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
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if (ret)
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return ret;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
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ret = regmap_update_bits(domain->reg_pull, reg,
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BIT(bit), 0);
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if (ret)
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return ret;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
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®, &bit);
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ret = regmap_update_bits(domain->reg_pullen, reg,
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BIT(bit), BIT(bit));
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
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ret = regmap_update_bits(domain->reg_pull, reg,
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BIT(bit), BIT(bit));
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if (ret)
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return ret;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
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®, &bit);
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ret = regmap_update_bits(domain->reg_pullen, reg,
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BIT(bit), BIT(bit));
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
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ret = regmap_update_bits(domain->reg_pull, reg,
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BIT(bit), 0);
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if (ret)
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return ret;
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break;
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default:
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return -ENOTSUPP;
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}
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}
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return 0;
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}
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static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
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{
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struct meson_domain *domain;
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struct meson_bank *bank;
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unsigned int reg, bit, val;
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int ret, conf;
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ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
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if (ret)
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return ret;
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meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit);
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ret = regmap_read(domain->reg_pullen, reg, &val);
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if (ret)
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return ret;
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if (!(val & BIT(bit))) {
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conf = PIN_CONFIG_BIAS_DISABLE;
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} else {
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meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit);
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ret = regmap_read(domain->reg_pull, reg, &val);
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if (ret)
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return ret;
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if (val & BIT(bit))
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conf = PIN_CONFIG_BIAS_PULL_UP;
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else
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conf = PIN_CONFIG_BIAS_PULL_DOWN;
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}
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return conf;
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}
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static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
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unsigned long *config)
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{
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struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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u16 arg;
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switch (param) {
|
|
case PIN_CONFIG_BIAS_DISABLE:
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
if (meson_pinconf_get_pull(pc, pin) == param)
|
|
arg = 1;
|
|
else
|
|
return -EINVAL;
|
|
break;
|
|
default:
|
|
return -ENOTSUPP;
|
|
}
|
|
|
|
*config = pinconf_to_config_packed(param, arg);
|
|
dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
|
|
unsigned int num_group,
|
|
unsigned long *configs, unsigned num_configs)
|
|
{
|
|
struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
|
|
struct meson_pmx_group *group = &pc->data->groups[num_group];
|
|
int i;
|
|
|
|
dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
|
|
|
|
for (i = 0; i < group->num_pins; i++) {
|
|
meson_pinconf_set(pcdev, group->pins[i], configs,
|
|
num_configs);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
|
|
unsigned int group, unsigned long *config)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static const struct pinconf_ops meson_pinconf_ops = {
|
|
.pin_config_get = meson_pinconf_get,
|
|
.pin_config_set = meson_pinconf_set,
|
|
.pin_config_group_get = meson_pinconf_group_get,
|
|
.pin_config_group_set = meson_pinconf_group_set,
|
|
.is_generic = true,
|
|
};
|
|
|
|
static inline struct meson_domain *to_meson_domain(struct gpio_chip *chip)
|
|
{
|
|
return container_of(chip, struct meson_domain, chip);
|
|
}
|
|
|
|
static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
|
|
{
|
|
return pinctrl_request_gpio(chip->base + gpio);
|
|
}
|
|
|
|
static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
|
|
{
|
|
struct meson_domain *domain = to_meson_domain(chip);
|
|
|
|
pinctrl_free_gpio(domain->data->pin_base + gpio);
|
|
}
|
|
|
|
static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
|
|
{
|
|
struct meson_domain *domain = to_meson_domain(chip);
|
|
unsigned int reg, bit, pin;
|
|
struct meson_bank *bank;
|
|
int ret;
|
|
|
|
pin = domain->data->pin_base + gpio;
|
|
ret = meson_get_bank(domain, pin, &bank);
|
|
if (ret)
|
|
return ret;
|
|
|
|
meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
|
|
|
|
return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit));
|
|
}
|
|
|
|
static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
|
|
int value)
|
|
{
|
|
struct meson_domain *domain = to_meson_domain(chip);
|
|
unsigned int reg, bit, pin;
|
|
struct meson_bank *bank;
|
|
int ret;
|
|
|
|
pin = domain->data->pin_base + gpio;
|
|
ret = meson_get_bank(domain, pin, &bank);
|
|
if (ret)
|
|
return ret;
|
|
|
|
meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit);
|
|
ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
|
|
return regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
|
|
value ? BIT(bit) : 0);
|
|
}
|
|
|
|
static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
|
|
{
|
|
struct meson_domain *domain = to_meson_domain(chip);
|
|
unsigned int reg, bit, pin;
|
|
struct meson_bank *bank;
|
|
int ret;
|
|
|
|
pin = domain->data->pin_base + gpio;
|
|
ret = meson_get_bank(domain, pin, &bank);
|
|
if (ret)
|
|
return;
|
|
|
|
meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit);
|
|
regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
|
|
value ? BIT(bit) : 0);
|
|
}
|
|
|
|
static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
|
|
{
|
|
struct meson_domain *domain = to_meson_domain(chip);
|
|
unsigned int reg, bit, val, pin;
|
|
struct meson_bank *bank;
|
|
int ret;
|
|
|
|
pin = domain->data->pin_base + gpio;
|
|
ret = meson_get_bank(domain, pin, &bank);
|
|
if (ret)
|
|
return ret;
|
|
|
|
meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit);
|
|
regmap_read(domain->reg_gpio, reg, &val);
|
|
|
|
return !!(val & BIT(bit));
|
|
}
|
|
|
|
static const struct of_device_id meson_pinctrl_dt_match[] = {
|
|
{
|
|
.compatible = "amlogic,meson8-pinctrl",
|
|
.data = &meson8_pinctrl_data,
|
|
},
|
|
{
|
|
.compatible = "amlogic,meson8b-pinctrl",
|
|
.data = &meson8b_pinctrl_data,
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
|
|
|
|
static int meson_gpiolib_register(struct meson_pinctrl *pc)
|
|
{
|
|
struct meson_domain *domain;
|
|
int i, ret;
|
|
|
|
for (i = 0; i < pc->data->num_domains; i++) {
|
|
domain = &pc->domains[i];
|
|
|
|
domain->chip.label = domain->data->name;
|
|
domain->chip.dev = pc->dev;
|
|
domain->chip.request = meson_gpio_request;
|
|
domain->chip.free = meson_gpio_free;
|
|
domain->chip.direction_input = meson_gpio_direction_input;
|
|
domain->chip.direction_output = meson_gpio_direction_output;
|
|
domain->chip.get = meson_gpio_get;
|
|
domain->chip.set = meson_gpio_set;
|
|
domain->chip.base = domain->data->pin_base;
|
|
domain->chip.ngpio = domain->data->num_pins;
|
|
domain->chip.can_sleep = false;
|
|
domain->chip.of_node = domain->of_node;
|
|
domain->chip.of_gpio_n_cells = 2;
|
|
|
|
ret = gpiochip_add(&domain->chip);
|
|
if (ret) {
|
|
dev_err(pc->dev, "can't add gpio chip %s\n",
|
|
domain->data->name);
|
|
goto fail;
|
|
}
|
|
|
|
ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
|
|
0, domain->data->pin_base,
|
|
domain->chip.ngpio);
|
|
if (ret) {
|
|
dev_err(pc->dev, "can't add pin range\n");
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
fail:
|
|
for (i--; i >= 0; i--)
|
|
gpiochip_remove(&pc->domains[i].chip);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc,
|
|
struct device_node *np)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < pc->data->num_domains; i++) {
|
|
if (!strcmp(np->name, pc->data->domain_data[i].name))
|
|
return &pc->data->domain_data[i];
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static struct regmap_config meson_regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
};
|
|
|
|
static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
|
|
struct device_node *node, char *name)
|
|
{
|
|
struct resource res;
|
|
void __iomem *base;
|
|
int i;
|
|
|
|
i = of_property_match_string(node, "reg-names", name);
|
|
if (of_address_to_resource(node, i, &res))
|
|
return ERR_PTR(-ENOENT);
|
|
|
|
base = devm_ioremap_resource(pc->dev, &res);
|
|
if (IS_ERR(base))
|
|
return ERR_CAST(base);
|
|
|
|
meson_regmap_config.max_register = resource_size(&res) - 4;
|
|
meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
|
|
"%s-%s", node->name,
|
|
name);
|
|
if (!meson_regmap_config.name)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
|
|
}
|
|
|
|
static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
|
|
struct device_node *node)
|
|
{
|
|
struct device_node *np;
|
|
struct meson_domain *domain;
|
|
int i = 0, num_domains = 0;
|
|
|
|
for_each_child_of_node(node, np) {
|
|
if (!of_find_property(np, "gpio-controller", NULL))
|
|
continue;
|
|
num_domains++;
|
|
}
|
|
|
|
if (num_domains != pc->data->num_domains) {
|
|
dev_err(pc->dev, "wrong number of subnodes\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pc->domains = devm_kzalloc(pc->dev, num_domains *
|
|
sizeof(struct meson_domain), GFP_KERNEL);
|
|
if (!pc->domains)
|
|
return -ENOMEM;
|
|
|
|
for_each_child_of_node(node, np) {
|
|
if (!of_find_property(np, "gpio-controller", NULL))
|
|
continue;
|
|
|
|
domain = &pc->domains[i];
|
|
|
|
domain->data = meson_get_domain_data(pc, np);
|
|
if (!domain->data) {
|
|
dev_err(pc->dev, "domain data not found for node %s\n",
|
|
np->name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
domain->of_node = np;
|
|
|
|
domain->reg_mux = meson_map_resource(pc, np, "mux");
|
|
if (IS_ERR(domain->reg_mux)) {
|
|
dev_err(pc->dev, "mux registers not found\n");
|
|
return PTR_ERR(domain->reg_mux);
|
|
}
|
|
|
|
domain->reg_pull = meson_map_resource(pc, np, "pull");
|
|
if (IS_ERR(domain->reg_pull)) {
|
|
dev_err(pc->dev, "pull registers not found\n");
|
|
return PTR_ERR(domain->reg_pull);
|
|
}
|
|
|
|
domain->reg_pullen = meson_map_resource(pc, np, "pull-enable");
|
|
/* Use pull region if pull-enable one is not present */
|
|
if (IS_ERR(domain->reg_pullen))
|
|
domain->reg_pullen = domain->reg_pull;
|
|
|
|
domain->reg_gpio = meson_map_resource(pc, np, "gpio");
|
|
if (IS_ERR(domain->reg_gpio)) {
|
|
dev_err(pc->dev, "gpio registers not found\n");
|
|
return PTR_ERR(domain->reg_gpio);
|
|
}
|
|
|
|
i++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int meson_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct device *dev = &pdev->dev;
|
|
struct meson_pinctrl *pc;
|
|
int ret;
|
|
|
|
pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
|
|
if (!pc)
|
|
return -ENOMEM;
|
|
|
|
pc->dev = dev;
|
|
match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
|
|
pc->data = (struct meson_pinctrl_data *)match->data;
|
|
|
|
ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pc->desc.name = "pinctrl-meson";
|
|
pc->desc.owner = THIS_MODULE;
|
|
pc->desc.pctlops = &meson_pctrl_ops;
|
|
pc->desc.pmxops = &meson_pmx_ops;
|
|
pc->desc.confops = &meson_pinconf_ops;
|
|
pc->desc.pins = pc->data->pins;
|
|
pc->desc.npins = pc->data->num_pins;
|
|
|
|
pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc);
|
|
if (IS_ERR(pc->pcdev)) {
|
|
dev_err(pc->dev, "can't register pinctrl device");
|
|
return PTR_ERR(pc->pcdev);
|
|
}
|
|
|
|
ret = meson_gpiolib_register(pc);
|
|
if (ret) {
|
|
pinctrl_unregister(pc->pcdev);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver meson_pinctrl_driver = {
|
|
.probe = meson_pinctrl_probe,
|
|
.driver = {
|
|
.name = "meson-pinctrl",
|
|
.of_match_table = meson_pinctrl_dt_match,
|
|
},
|
|
};
|
|
module_platform_driver(meson_pinctrl_driver);
|
|
|
|
MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
|
|
MODULE_DESCRIPTION("Amlogic Meson pinctrl driver");
|
|
MODULE_LICENSE("GPL v2");
|