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![Laurent Pinchart](/assets/img/avatar_default.png)
Now that all ARM-based Renesas SoCs use multiplatform kernels only the hardcoded IRQ numbers can be dropped as they're dynamically allocated. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
420 lines
9.6 KiB
C
420 lines
9.6 KiB
C
/*
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* SuperH Pin Function Controller GPIO driver.
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*
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* Copyright (C) 2008 Magnus Damm
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* Copyright (C) 2009 - 2012 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "core.h"
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struct sh_pfc_gpio_data_reg {
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const struct pinmux_data_reg *info;
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u32 shadow;
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};
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struct sh_pfc_gpio_pin {
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u8 dbit;
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u8 dreg;
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};
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struct sh_pfc_chip {
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struct sh_pfc *pfc;
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struct gpio_chip gpio_chip;
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struct sh_pfc_window *mem;
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struct sh_pfc_gpio_data_reg *regs;
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struct sh_pfc_gpio_pin *pins;
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};
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static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
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{
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return container_of(gc, struct sh_pfc_chip, gpio_chip);
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}
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static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
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{
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return gpio_to_pfc_chip(gc)->pfc;
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}
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static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
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struct sh_pfc_gpio_data_reg **reg,
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unsigned int *bit)
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{
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int idx = sh_pfc_get_pin_index(chip->pfc, offset);
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struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
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*reg = &chip->regs[gpio_pin->dreg];
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*bit = gpio_pin->dbit;
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}
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static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
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const struct pinmux_data_reg *dreg)
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{
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phys_addr_t address = dreg->reg;
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void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
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return sh_pfc_read_raw_reg(mem, dreg->reg_width);
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}
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static void gpio_write_data_reg(struct sh_pfc_chip *chip,
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const struct pinmux_data_reg *dreg, u32 value)
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{
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phys_addr_t address = dreg->reg;
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void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
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sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
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}
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static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
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{
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struct sh_pfc *pfc = chip->pfc;
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struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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const struct pinmux_data_reg *dreg;
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unsigned int bit;
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unsigned int i;
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for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
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for (bit = 0; bit < dreg->reg_width; bit++) {
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if (dreg->enum_ids[bit] == pin->enum_id) {
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gpio_pin->dreg = i;
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gpio_pin->dbit = bit;
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return;
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}
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}
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}
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BUG();
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}
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static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
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{
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struct sh_pfc *pfc = chip->pfc;
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const struct pinmux_data_reg *dreg;
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unsigned int i;
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/* Count the number of data registers, allocate memory and initialize
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* them.
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*/
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for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
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;
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chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
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GFP_KERNEL);
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if (chip->regs == NULL)
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return -ENOMEM;
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for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
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chip->regs[i].info = dreg;
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chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
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}
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for (i = 0; i < pfc->info->nr_pins; i++) {
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if (pfc->info->pins[i].enum_id == 0)
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continue;
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gpio_setup_data_reg(chip, i);
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}
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return 0;
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}
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/* -----------------------------------------------------------------------------
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* Pin GPIOs
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*/
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static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
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{
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struct sh_pfc *pfc = gpio_to_pfc(gc);
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int idx = sh_pfc_get_pin_index(pfc, offset);
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if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
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return -EINVAL;
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return pinctrl_request_gpio(offset);
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}
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static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
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{
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return pinctrl_free_gpio(offset);
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}
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static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
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int value)
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{
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struct sh_pfc_gpio_data_reg *reg;
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unsigned int bit;
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unsigned int pos;
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gpio_get_data_reg(chip, offset, ®, &bit);
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pos = reg->info->reg_width - (bit + 1);
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if (value)
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reg->shadow |= BIT(pos);
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else
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reg->shadow &= ~BIT(pos);
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gpio_write_data_reg(chip, reg->info, reg->shadow);
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}
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static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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return pinctrl_gpio_direction_input(offset);
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}
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static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
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int value)
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{
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gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
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return pinctrl_gpio_direction_output(offset);
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}
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static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
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{
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struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
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struct sh_pfc_gpio_data_reg *reg;
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unsigned int bit;
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unsigned int pos;
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gpio_get_data_reg(chip, offset, ®, &bit);
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pos = reg->info->reg_width - (bit + 1);
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return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
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}
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static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
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{
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gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
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}
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static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct sh_pfc *pfc = gpio_to_pfc(gc);
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unsigned int i, k;
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for (i = 0; i < pfc->info->gpio_irq_size; i++) {
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const short *gpios = pfc->info->gpio_irq[i].gpios;
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for (k = 0; gpios[k] >= 0; k++) {
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if (gpios[k] == offset)
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goto found;
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}
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}
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return -ENOSYS;
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found:
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return pfc->irqs[i];
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}
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static int gpio_pin_setup(struct sh_pfc_chip *chip)
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{
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struct sh_pfc *pfc = chip->pfc;
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struct gpio_chip *gc = &chip->gpio_chip;
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int ret;
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chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins *
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sizeof(*chip->pins), GFP_KERNEL);
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if (chip->pins == NULL)
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return -ENOMEM;
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ret = gpio_setup_data_regs(chip);
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if (ret < 0)
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return ret;
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gc->request = gpio_pin_request;
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gc->free = gpio_pin_free;
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gc->direction_input = gpio_pin_direction_input;
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gc->get = gpio_pin_get;
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gc->direction_output = gpio_pin_direction_output;
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gc->set = gpio_pin_set;
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gc->to_irq = gpio_pin_to_irq;
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gc->label = pfc->info->name;
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gc->dev = pfc->dev;
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gc->owner = THIS_MODULE;
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gc->base = 0;
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gc->ngpio = pfc->nr_gpio_pins;
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return 0;
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}
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/* -----------------------------------------------------------------------------
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* Function GPIOs
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*/
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#ifdef CONFIG_SUPERH
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static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
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{
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static bool __print_once;
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struct sh_pfc *pfc = gpio_to_pfc(gc);
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unsigned int mark = pfc->info->func_gpios[offset].enum_id;
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unsigned long flags;
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int ret;
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if (!__print_once) {
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dev_notice(pfc->dev,
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"Use of GPIO API for function requests is deprecated."
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" Convert to pinctrl\n");
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__print_once = true;
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}
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if (mark == 0)
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return -EINVAL;
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spin_lock_irqsave(&pfc->lock, flags);
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ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
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spin_unlock_irqrestore(&pfc->lock, flags);
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return ret;
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}
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static int gpio_function_setup(struct sh_pfc_chip *chip)
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{
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struct sh_pfc *pfc = chip->pfc;
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struct gpio_chip *gc = &chip->gpio_chip;
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gc->request = gpio_function_request;
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gc->label = pfc->info->name;
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gc->owner = THIS_MODULE;
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gc->base = pfc->nr_gpio_pins;
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gc->ngpio = pfc->info->nr_func_gpios;
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return 0;
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}
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#endif
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/* -----------------------------------------------------------------------------
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* Register/unregister
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*/
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static struct sh_pfc_chip *
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sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
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struct sh_pfc_window *mem)
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{
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struct sh_pfc_chip *chip;
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int ret;
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chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
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if (unlikely(!chip))
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return ERR_PTR(-ENOMEM);
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chip->mem = mem;
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chip->pfc = pfc;
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ret = setup(chip);
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if (ret < 0)
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return ERR_PTR(ret);
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ret = gpiochip_add(&chip->gpio_chip);
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if (unlikely(ret < 0))
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return ERR_PTR(ret);
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dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
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chip->gpio_chip.label, chip->gpio_chip.base,
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chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
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return chip;
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}
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int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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{
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struct sh_pfc_chip *chip;
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phys_addr_t address;
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unsigned int i;
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if (pfc->info->data_regs == NULL)
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return 0;
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/* Find the memory window that contain the GPIO registers. Boards that
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* register a separate GPIO device will not supply a memory resource
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* that covers the data registers. In that case don't try to handle
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* GPIOs.
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*/
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address = pfc->info->data_regs[0].reg;
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for (i = 0; i < pfc->num_windows; ++i) {
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struct sh_pfc_window *window = &pfc->windows[i];
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if (address >= window->phys &&
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address < window->phys + window->size)
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break;
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}
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if (i == pfc->num_windows)
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return 0;
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/* If we have IRQ resources make sure their number is correct. */
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if (pfc->num_irqs != pfc->info->gpio_irq_size) {
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dev_err(pfc->dev, "invalid number of IRQ resources\n");
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return -EINVAL;
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}
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/* Register the real GPIOs chip. */
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chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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pfc->gpio = chip;
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if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
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return 0;
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#ifdef CONFIG_SUPERH
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/*
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* Register the GPIO to pin mappings. As pins with GPIO ports
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* must come first in the ranges, skip the pins without GPIO
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* ports by stopping at the first range that contains such a
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* pin.
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*/
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for (i = 0; i < pfc->nr_ranges; ++i) {
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const struct sh_pfc_pin_range *range = &pfc->ranges[i];
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int ret;
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if (range->start >= pfc->nr_gpio_pins)
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break;
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ret = gpiochip_add_pin_range(&chip->gpio_chip,
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dev_name(pfc->dev), range->start, range->start,
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range->end - range->start + 1);
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if (ret < 0)
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return ret;
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}
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/* Register the function GPIOs chip. */
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if (pfc->info->nr_func_gpios == 0)
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return 0;
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chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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pfc->func = chip;
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#endif /* CONFIG_SUPERH */
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return 0;
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}
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int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
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{
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gpiochip_remove(&pfc->gpio->gpio_chip);
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#ifdef CONFIG_SUPERH
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gpiochip_remove(&pfc->func->gpio_chip);
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#endif
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return 0;
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}
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