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![Anshuman Khandual](/assets/img/avatar_default.png)
Add support for dedicated sinks that are bound to individual CPUs. (e.g, TRBE). To allow quicker access to the sink for a given CPU bound source, keep a percpu array of the sink devices. Also, add support for building a path to the CPU local sink from the ETM. This adds a new percpu sink type CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM. This new sink type is exclusively available and can only work with percpu source type device CORESIGHT_DEV_SUBTYPE_SOURCE_PROC. This defines a percpu structure that accommodates a single coresight_device which can be used to store an initialized instance from a sink driver. As these sinks are exclusively linked and dependent on corresponding percpu sources devices, they should also be the default sink device during a perf session. Outwards device connections are scanned while establishing paths between a source and a sink device. But such connections are not present for certain percpu source and sink devices which are exclusively linked and dependent. Build the path directly and skip connection scanning for such devices. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> [Moved the set/get percpu sink APIs from TRBE patch to here Fixed build break on arm32] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20210405164307.1720226-17-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
581 lines
17 KiB
C
581 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2012, The Linux Foundation. All rights reserved.
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*/
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#ifndef _LINUX_CORESIGHT_H
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#define _LINUX_CORESIGHT_H
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/perf_event.h>
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#include <linux/sched.h>
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/* Peripheral id registers (0xFD0-0xFEC) */
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#define CORESIGHT_PERIPHIDR4 0xfd0
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#define CORESIGHT_PERIPHIDR5 0xfd4
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#define CORESIGHT_PERIPHIDR6 0xfd8
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#define CORESIGHT_PERIPHIDR7 0xfdC
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#define CORESIGHT_PERIPHIDR0 0xfe0
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#define CORESIGHT_PERIPHIDR1 0xfe4
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#define CORESIGHT_PERIPHIDR2 0xfe8
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#define CORESIGHT_PERIPHIDR3 0xfeC
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/* Component id registers (0xFF0-0xFFC) */
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#define CORESIGHT_COMPIDR0 0xff0
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#define CORESIGHT_COMPIDR1 0xff4
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#define CORESIGHT_COMPIDR2 0xff8
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#define CORESIGHT_COMPIDR3 0xffC
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#define ETM_ARCH_V3_3 0x23
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#define ETM_ARCH_V3_5 0x25
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#define PFT_ARCH_V1_0 0x30
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#define PFT_ARCH_V1_1 0x31
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#define CORESIGHT_UNLOCK 0xc5acce55
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extern struct bus_type coresight_bustype;
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enum coresight_dev_type {
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CORESIGHT_DEV_TYPE_NONE,
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CORESIGHT_DEV_TYPE_SINK,
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CORESIGHT_DEV_TYPE_LINK,
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CORESIGHT_DEV_TYPE_LINKSINK,
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CORESIGHT_DEV_TYPE_SOURCE,
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CORESIGHT_DEV_TYPE_HELPER,
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CORESIGHT_DEV_TYPE_ECT,
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};
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enum coresight_dev_subtype_sink {
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CORESIGHT_DEV_SUBTYPE_SINK_NONE,
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CORESIGHT_DEV_SUBTYPE_SINK_PORT,
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CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
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CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
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CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
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};
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enum coresight_dev_subtype_link {
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CORESIGHT_DEV_SUBTYPE_LINK_NONE,
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CORESIGHT_DEV_SUBTYPE_LINK_MERG,
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CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
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CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
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};
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enum coresight_dev_subtype_source {
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CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
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CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
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CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
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CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
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};
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enum coresight_dev_subtype_helper {
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CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
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CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
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};
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/* Embedded Cross Trigger (ECT) sub-types */
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enum coresight_dev_subtype_ect {
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CORESIGHT_DEV_SUBTYPE_ECT_NONE,
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CORESIGHT_DEV_SUBTYPE_ECT_CTI,
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};
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/**
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* union coresight_dev_subtype - further characterisation of a type
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* @sink_subtype: type of sink this component is, as defined
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* by @coresight_dev_subtype_sink.
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* @link_subtype: type of link this component is, as defined
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* by @coresight_dev_subtype_link.
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* @source_subtype: type of source this component is, as defined
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* by @coresight_dev_subtype_source.
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* @helper_subtype: type of helper this component is, as defined
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* by @coresight_dev_subtype_helper.
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* @ect_subtype: type of cross trigger this component is, as
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* defined by @coresight_dev_subtype_ect
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*/
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union coresight_dev_subtype {
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/* We have some devices which acts as LINK and SINK */
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struct {
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enum coresight_dev_subtype_sink sink_subtype;
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enum coresight_dev_subtype_link link_subtype;
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};
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enum coresight_dev_subtype_source source_subtype;
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enum coresight_dev_subtype_helper helper_subtype;
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enum coresight_dev_subtype_ect ect_subtype;
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};
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/**
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* struct coresight_platform_data - data harvested from the firmware
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* specification.
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*
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* @nr_inport: Number of elements for the input connections.
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* @nr_outport: Number of elements for the output connections.
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* @conns: Sparse array of nr_outport connections from this component.
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*/
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struct coresight_platform_data {
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int nr_inport;
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int nr_outport;
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struct coresight_connection *conns;
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};
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/**
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* struct csdev_access - Abstraction of a CoreSight device access.
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*
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* @io_mem : True if the device has memory mapped I/O
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* @base : When io_mem == true, base address of the component
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* @read : Read from the given "offset" of the given instance.
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* @write : Write "val" to the given "offset".
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*/
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struct csdev_access {
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bool io_mem;
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union {
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void __iomem *base;
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struct {
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u64 (*read)(u32 offset, bool relaxed, bool _64bit);
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void (*write)(u64 val, u32 offset, bool relaxed,
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bool _64bit);
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};
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};
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};
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#define CSDEV_ACCESS_IOMEM(_addr) \
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((struct csdev_access) { \
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.io_mem = true, \
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.base = (_addr), \
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})
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/**
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* struct coresight_desc - description of a component required from drivers
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* @type: as defined by @coresight_dev_type.
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* @subtype: as defined by @coresight_dev_subtype.
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* @ops: generic operations for this component, as defined
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* by @coresight_ops.
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* @pdata: platform data collected from DT.
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* @dev: The device entity associated to this component.
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* @groups: operations specific to this component. These will end up
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* in the component's sysfs sub-directory.
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* @name: name for the coresight device, also shown under sysfs.
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* @access: Describe access to the device
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*/
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struct coresight_desc {
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enum coresight_dev_type type;
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union coresight_dev_subtype subtype;
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const struct coresight_ops *ops;
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struct coresight_platform_data *pdata;
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struct device *dev;
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const struct attribute_group **groups;
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const char *name;
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struct csdev_access access;
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};
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/**
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* struct coresight_connection - representation of a single connection
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* @outport: a connection's output port number.
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* @child_port: remote component's port number @output is connected to.
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* @chid_fwnode: remote component's fwnode handle.
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* @child_dev: a @coresight_device representation of the component
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connected to @outport.
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* @link: Representation of the connection as a sysfs link.
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*/
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struct coresight_connection {
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int outport;
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int child_port;
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struct fwnode_handle *child_fwnode;
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struct coresight_device *child_dev;
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struct coresight_sysfs_link *link;
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};
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/**
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* struct coresight_sysfs_link - representation of a connection in sysfs.
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* @orig: Originating (master) coresight device for the link.
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* @orig_name: Name to use for the link orig->target.
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* @target: Target (slave) coresight device for the link.
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* @target_name: Name to use for the link target->orig.
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*/
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struct coresight_sysfs_link {
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struct coresight_device *orig;
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const char *orig_name;
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struct coresight_device *target;
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const char *target_name;
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};
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/**
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* struct coresight_device - representation of a device as used by the framework
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* @pdata: Platform data with device connections associated to this device.
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* @type: as defined by @coresight_dev_type.
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* @subtype: as defined by @coresight_dev_subtype.
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* @ops: generic operations for this component, as defined
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* by @coresight_ops.
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* @access: Device i/o access abstraction for this device.
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* @dev: The device entity associated to this component.
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* @refcnt: keep track of what is in use.
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* @orphan: true if the component has connections that haven't been linked.
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* @enable: 'true' if component is currently part of an active path.
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* @activated: 'true' only if a _sink_ has been activated. A sink can be
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* activated but not yet enabled. Enabling for a _sink_
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* happens when a source has been selected and a path is enabled
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* from source to that sink.
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* @ea: Device attribute for sink representation under PMU directory.
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* @def_sink: cached reference to default sink found for this device.
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* @ect_dev: Associated cross trigger device. Not part of the trace data
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* path or connections.
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* @nr_links: number of sysfs links created to other components from this
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* device. These will appear in the "connections" group.
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* @has_conns_grp: Have added a "connections" group for sysfs links.
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*/
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struct coresight_device {
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struct coresight_platform_data *pdata;
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enum coresight_dev_type type;
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union coresight_dev_subtype subtype;
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const struct coresight_ops *ops;
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struct csdev_access access;
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struct device dev;
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atomic_t *refcnt;
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bool orphan;
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bool enable; /* true only if configured as part of a path */
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/* sink specific fields */
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bool activated; /* true only if a sink is part of a path */
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struct dev_ext_attribute *ea;
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struct coresight_device *def_sink;
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/* cross trigger handling */
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struct coresight_device *ect_dev;
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/* sysfs links between components */
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int nr_links;
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bool has_conns_grp;
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bool ect_enabled; /* true only if associated ect device is enabled */
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};
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/*
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* coresight_dev_list - Mapping for devices to "name" index for device
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* names.
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*
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* @nr_idx: Number of entries already allocated.
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* @pfx: Prefix pattern for device name.
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* @fwnode_list: Array of fwnode_handles associated with each allocated
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* index, upto nr_idx entries.
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*/
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struct coresight_dev_list {
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int nr_idx;
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const char *pfx;
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struct fwnode_handle **fwnode_list;
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};
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#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
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static struct coresight_dev_list (var) = { \
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.pfx = dev_pfx, \
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.nr_idx = 0, \
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.fwnode_list = NULL, \
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}
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#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
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#define source_ops(csdev) csdev->ops->source_ops
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#define sink_ops(csdev) csdev->ops->sink_ops
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#define link_ops(csdev) csdev->ops->link_ops
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#define helper_ops(csdev) csdev->ops->helper_ops
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#define ect_ops(csdev) csdev->ops->ect_ops
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/**
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* struct coresight_ops_sink - basic operations for a sink
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* Operations available for sinks
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* @enable: enables the sink.
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* @disable: disables the sink.
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* @alloc_buffer: initialises perf's ring buffer for trace collection.
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* @free_buffer: release memory allocated in @get_config.
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* @update_buffer: update buffer pointers after a trace session.
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*/
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struct coresight_ops_sink {
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int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
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int (*disable)(struct coresight_device *csdev);
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void *(*alloc_buffer)(struct coresight_device *csdev,
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struct perf_event *event, void **pages,
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int nr_pages, bool overwrite);
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void (*free_buffer)(void *config);
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unsigned long (*update_buffer)(struct coresight_device *csdev,
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struct perf_output_handle *handle,
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void *sink_config);
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};
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/**
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* struct coresight_ops_link - basic operations for a link
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* Operations available for links.
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* @enable: enables flow between iport and oport.
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* @disable: disables flow between iport and oport.
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*/
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struct coresight_ops_link {
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int (*enable)(struct coresight_device *csdev, int iport, int oport);
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void (*disable)(struct coresight_device *csdev, int iport, int oport);
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};
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/**
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* struct coresight_ops_source - basic operations for a source
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* Operations available for sources.
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* @cpu_id: returns the value of the CPU number this component
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* is associated to.
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* @trace_id: returns the value of the component's trace ID as known
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* to the HW.
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* @enable: enables tracing for a source.
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* @disable: disables tracing for a source.
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*/
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struct coresight_ops_source {
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int (*cpu_id)(struct coresight_device *csdev);
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int (*trace_id)(struct coresight_device *csdev);
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int (*enable)(struct coresight_device *csdev,
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struct perf_event *event, u32 mode);
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void (*disable)(struct coresight_device *csdev,
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struct perf_event *event);
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};
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/**
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* struct coresight_ops_helper - Operations for a helper device.
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*
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* All operations could pass in a device specific data, which could
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* help the helper device to determine what to do.
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*
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* @enable : Enable the device
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* @disable : Disable the device
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*/
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struct coresight_ops_helper {
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int (*enable)(struct coresight_device *csdev, void *data);
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int (*disable)(struct coresight_device *csdev, void *data);
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};
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/**
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* struct coresight_ops_ect - Ops for an embedded cross trigger device
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*
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* @enable : Enable the device
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* @disable : Disable the device
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*/
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struct coresight_ops_ect {
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int (*enable)(struct coresight_device *csdev);
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int (*disable)(struct coresight_device *csdev);
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};
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struct coresight_ops {
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const struct coresight_ops_sink *sink_ops;
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const struct coresight_ops_link *link_ops;
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const struct coresight_ops_source *source_ops;
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const struct coresight_ops_helper *helper_ops;
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const struct coresight_ops_ect *ect_ops;
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};
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#if IS_ENABLED(CONFIG_CORESIGHT)
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static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
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u32 offset)
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{
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if (likely(csa->io_mem))
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return readl_relaxed(csa->base + offset);
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return csa->read(offset, true, false);
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}
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static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
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{
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if (likely(csa->io_mem))
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return readl(csa->base + offset);
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return csa->read(offset, false, false);
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}
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static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
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u32 val, u32 offset)
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{
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if (likely(csa->io_mem))
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writel_relaxed(val, csa->base + offset);
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else
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csa->write(val, offset, true, false);
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}
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static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
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{
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if (likely(csa->io_mem))
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writel(val, csa->base + offset);
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else
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csa->write(val, offset, false, false);
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}
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#ifdef CONFIG_64BIT
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static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
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u32 offset)
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{
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if (likely(csa->io_mem))
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return readq_relaxed(csa->base + offset);
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return csa->read(offset, true, true);
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}
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static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
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{
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if (likely(csa->io_mem))
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return readq(csa->base + offset);
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return csa->read(offset, false, true);
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}
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static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
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u64 val, u32 offset)
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{
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if (likely(csa->io_mem))
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writeq_relaxed(val, csa->base + offset);
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else
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csa->write(val, offset, true, true);
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}
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static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
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{
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if (likely(csa->io_mem))
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writeq(val, csa->base + offset);
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else
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csa->write(val, offset, false, true);
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}
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#else /* !CONFIG_64BIT */
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static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
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u32 offset)
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{
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WARN_ON(1);
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return 0;
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}
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static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
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{
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WARN_ON(1);
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return 0;
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}
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static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
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u64 val, u32 offset)
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{
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WARN_ON(1);
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}
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static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
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{
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WARN_ON(1);
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}
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#endif /* CONFIG_64BIT */
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static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
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{
|
|
return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
|
|
(csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
|
|
}
|
|
|
|
static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
|
|
{
|
|
return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
|
|
(csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
|
|
}
|
|
|
|
extern struct coresight_device *
|
|
coresight_register(struct coresight_desc *desc);
|
|
extern void coresight_unregister(struct coresight_device *csdev);
|
|
extern int coresight_enable(struct coresight_device *csdev);
|
|
extern void coresight_disable(struct coresight_device *csdev);
|
|
extern int coresight_timeout(struct csdev_access *csa, u32 offset,
|
|
int position, int value);
|
|
|
|
extern int coresight_claim_device(struct coresight_device *csdev);
|
|
extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
|
|
|
|
extern void coresight_disclaim_device(struct coresight_device *csdev);
|
|
extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
|
|
extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
|
|
struct device *dev);
|
|
|
|
extern bool coresight_loses_context_with_cpu(struct device *dev);
|
|
|
|
u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
|
|
u32 coresight_read32(struct coresight_device *csdev, u32 offset);
|
|
void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
|
|
void coresight_relaxed_write32(struct coresight_device *csdev,
|
|
u32 val, u32 offset);
|
|
u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
|
|
u64 coresight_read64(struct coresight_device *csdev, u32 offset);
|
|
void coresight_relaxed_write64(struct coresight_device *csdev,
|
|
u64 val, u32 offset);
|
|
void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
|
|
|
|
#else
|
|
static inline struct coresight_device *
|
|
coresight_register(struct coresight_desc *desc) { return NULL; }
|
|
static inline void coresight_unregister(struct coresight_device *csdev) {}
|
|
static inline int
|
|
coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
|
|
static inline void coresight_disable(struct coresight_device *csdev) {}
|
|
|
|
static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
|
|
int position, int value)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static inline int coresight_claim_device(struct coresight_device *csdev)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
|
|
static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
|
|
|
|
static inline bool coresight_loses_context_with_cpu(struct device *dev)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
|
|
{
|
|
WARN_ON_ONCE(1);
|
|
return 0;
|
|
}
|
|
|
|
static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
|
|
{
|
|
WARN_ON_ONCE(1);
|
|
return 0;
|
|
}
|
|
|
|
static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
|
|
{
|
|
}
|
|
|
|
static inline void coresight_relaxed_write32(struct coresight_device *csdev,
|
|
u32 val, u32 offset)
|
|
{
|
|
}
|
|
|
|
static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
|
|
u32 offset)
|
|
{
|
|
WARN_ON_ONCE(1);
|
|
return 0;
|
|
}
|
|
|
|
static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
|
|
{
|
|
WARN_ON_ONCE(1);
|
|
return 0;
|
|
}
|
|
|
|
static inline void coresight_relaxed_write64(struct coresight_device *csdev,
|
|
u64 val, u32 offset)
|
|
{
|
|
}
|
|
|
|
static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
|
|
{
|
|
}
|
|
|
|
#endif /* IS_ENABLED(CONFIG_CORESIGHT) */
|
|
|
|
extern int coresight_get_cpu(struct device *dev);
|
|
|
|
struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
|
|
|
|
#endif /* _LINUX_COREISGHT_H */
|