Vladimir Zapolskiy e02a5d1d5a clk: lpc32xx: add a quirk for PWM and MS clock dividers ... [ Upstream commit f84d42a9cf ] In common clock framework CLK_DIVIDER_ONE_BASED or'ed with CLK_DIVIDER_ALLOW_ZERO flags indicates that 1) a divider clock may be set to zero value, 2) divider's zero value is interpreted as a non-divided clock. On the LPC32xx platform clock dividers of PWM and memory card clocks comply with the first condition, but zero value means a gated clock, thus it may happen that the divider value is not updated when the clock is enabled and the clock remains gated. The change adds one-shot quirks, which check for zero value of divider on initialization and set it to a non-zero value, therefore in runtime a gate clock will work as expected. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2017-04-12 12:41:15 +02:00
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Makefile	clk: add lpc18xx creg clk driver	2016-03-04 12:52:10 -08:00
clk-lpc18xx-ccu.c	clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h	2016-01-29 12:59:50 -08:00
clk-lpc18xx-cgu.c	clk: nxp: Remove CLK_IS_ROOT	2016-03-02 17:45:22 -08:00
clk-lpc18xx-creg.c	clk: nxp: Use new macro CLK_OF_DECLARE_DRIVER	2016-08-12 18:00:48 -07:00
clk-lpc32xx.c	clk: lpc32xx: add a quirk for PWM and MS clock dividers	2017-04-12 12:41:15 +02:00