502 lines
17 KiB
ArmAsm
502 lines
17 KiB
ArmAsm
// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// +build go1.7,amd64,!gccgo,!appengine
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#include "textflag.h"
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DATA ·AVX2_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908
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DATA ·AVX2_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b
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DATA ·AVX2_iv0<>+0x10(SB)/8, $0x3c6ef372fe94f82b
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DATA ·AVX2_iv0<>+0x18(SB)/8, $0xa54ff53a5f1d36f1
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GLOBL ·AVX2_iv0<>(SB), (NOPTR+RODATA), $32
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DATA ·AVX2_iv1<>+0x00(SB)/8, $0x510e527fade682d1
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DATA ·AVX2_iv1<>+0x08(SB)/8, $0x9b05688c2b3e6c1f
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DATA ·AVX2_iv1<>+0x10(SB)/8, $0x1f83d9abfb41bd6b
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DATA ·AVX2_iv1<>+0x18(SB)/8, $0x5be0cd19137e2179
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GLOBL ·AVX2_iv1<>(SB), (NOPTR+RODATA), $32
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DATA ·AVX2_c40<>+0x00(SB)/8, $0x0201000706050403
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DATA ·AVX2_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b
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DATA ·AVX2_c40<>+0x10(SB)/8, $0x0201000706050403
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DATA ·AVX2_c40<>+0x18(SB)/8, $0x0a09080f0e0d0c0b
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GLOBL ·AVX2_c40<>(SB), (NOPTR+RODATA), $32
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DATA ·AVX2_c48<>+0x00(SB)/8, $0x0100070605040302
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DATA ·AVX2_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a
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DATA ·AVX2_c48<>+0x10(SB)/8, $0x0100070605040302
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DATA ·AVX2_c48<>+0x18(SB)/8, $0x09080f0e0d0c0b0a
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GLOBL ·AVX2_c48<>(SB), (NOPTR+RODATA), $32
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DATA ·AVX_iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908
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DATA ·AVX_iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b
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GLOBL ·AVX_iv0<>(SB), (NOPTR+RODATA), $16
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DATA ·AVX_iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b
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DATA ·AVX_iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1
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GLOBL ·AVX_iv1<>(SB), (NOPTR+RODATA), $16
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DATA ·AVX_iv2<>+0x00(SB)/8, $0x510e527fade682d1
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DATA ·AVX_iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f
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GLOBL ·AVX_iv2<>(SB), (NOPTR+RODATA), $16
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DATA ·AVX_iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b
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DATA ·AVX_iv3<>+0x08(SB)/8, $0x5be0cd19137e2179
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GLOBL ·AVX_iv3<>(SB), (NOPTR+RODATA), $16
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DATA ·AVX_c40<>+0x00(SB)/8, $0x0201000706050403
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DATA ·AVX_c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b
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GLOBL ·AVX_c40<>(SB), (NOPTR+RODATA), $16
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DATA ·AVX_c48<>+0x00(SB)/8, $0x0100070605040302
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DATA ·AVX_c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a
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GLOBL ·AVX_c48<>(SB), (NOPTR+RODATA), $16
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// unfortunately the BYTE representation of VPERMQ must be used
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#define ROUND_AVX2(m0, m1, m2, m3, t, c40, c48) \
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VPADDQ m0, Y0, Y0; \
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VPADDQ Y1, Y0, Y0; \
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VPXOR Y0, Y3, Y3; \
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VPSHUFD $-79, Y3, Y3; \
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VPADDQ Y3, Y2, Y2; \
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VPXOR Y2, Y1, Y1; \
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VPSHUFB c40, Y1, Y1; \
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VPADDQ m1, Y0, Y0; \
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VPADDQ Y1, Y0, Y0; \
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VPXOR Y0, Y3, Y3; \
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VPSHUFB c48, Y3, Y3; \
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VPADDQ Y3, Y2, Y2; \
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VPXOR Y2, Y1, Y1; \
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VPADDQ Y1, Y1, t; \
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VPSRLQ $63, Y1, Y1; \
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VPXOR t, Y1, Y1; \
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BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x39 \ // VPERMQ 0x39, Y1, Y1
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BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xd2; BYTE $0x4e \ // VPERMQ 0x4e, Y2, Y2
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BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x93 \ // VPERMQ 0x93, Y3, Y3
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VPADDQ m2, Y0, Y0; \
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VPADDQ Y1, Y0, Y0; \
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VPXOR Y0, Y3, Y3; \
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VPSHUFD $-79, Y3, Y3; \
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VPADDQ Y3, Y2, Y2; \
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VPXOR Y2, Y1, Y1; \
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VPSHUFB c40, Y1, Y1; \
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VPADDQ m3, Y0, Y0; \
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VPADDQ Y1, Y0, Y0; \
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VPXOR Y0, Y3, Y3; \
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VPSHUFB c48, Y3, Y3; \
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VPADDQ Y3, Y2, Y2; \
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VPXOR Y2, Y1, Y1; \
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VPADDQ Y1, Y1, t; \
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VPSRLQ $63, Y1, Y1; \
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VPXOR t, Y1, Y1; \
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BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xdb; BYTE $0x39 \ // VPERMQ 0x39, Y3, Y3
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BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xd2; BYTE $0x4e \ // VPERMQ 0x4e, Y2, Y2
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BYTE $0xc4; BYTE $0xe3; BYTE $0xfd; BYTE $0x00; BYTE $0xc9; BYTE $0x93 \ // VPERMQ 0x93, Y1, Y1
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// load msg into Y12, Y13, Y14, Y15
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#define LOAD_MSG_AVX2(src, i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15) \
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MOVQ i0*8(src), X12; \
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PINSRQ $1, i1*8(src), X12; \
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MOVQ i2*8(src), X11; \
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PINSRQ $1, i3*8(src), X11; \
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VINSERTI128 $1, X11, Y12, Y12; \
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MOVQ i4*8(src), X13; \
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PINSRQ $1, i5*8(src), X13; \
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MOVQ i6*8(src), X11; \
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PINSRQ $1, i7*8(src), X11; \
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VINSERTI128 $1, X11, Y13, Y13; \
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MOVQ i8*8(src), X14; \
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PINSRQ $1, i9*8(src), X14; \
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MOVQ i10*8(src), X11; \
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PINSRQ $1, i11*8(src), X11; \
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VINSERTI128 $1, X11, Y14, Y14; \
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MOVQ i12*8(src), X15; \
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PINSRQ $1, i13*8(src), X15; \
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MOVQ i14*8(src), X11; \
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PINSRQ $1, i15*8(src), X11; \
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VINSERTI128 $1, X11, Y15, Y15
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// func hashBlocksAVX2(h *[8]uint64, c *[2]uint64, flag uint64, blocks []byte)
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TEXT ·hashBlocksAVX2(SB), 4, $320-48 // frame size = 288 + 32 byte alignment
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MOVQ h+0(FP), AX
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MOVQ c+8(FP), BX
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MOVQ flag+16(FP), CX
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MOVQ blocks_base+24(FP), SI
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MOVQ blocks_len+32(FP), DI
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MOVQ SP, DX
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MOVQ SP, R9
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ADDQ $31, R9
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ANDQ $~31, R9
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MOVQ R9, SP
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MOVQ CX, 16(SP)
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XORQ CX, CX
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MOVQ CX, 24(SP)
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VMOVDQU ·AVX2_c40<>(SB), Y4
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VMOVDQU ·AVX2_c48<>(SB), Y5
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VMOVDQU 0(AX), Y8
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VMOVDQU 32(AX), Y9
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VMOVDQU ·AVX2_iv0<>(SB), Y6
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VMOVDQU ·AVX2_iv1<>(SB), Y7
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MOVQ 0(BX), R8
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MOVQ 8(BX), R9
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MOVQ R9, 8(SP)
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loop:
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ADDQ $128, R8
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MOVQ R8, 0(SP)
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CMPQ R8, $128
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JGE noinc
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INCQ R9
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MOVQ R9, 8(SP)
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noinc:
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VMOVDQA Y8, Y0
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VMOVDQA Y9, Y1
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VMOVDQA Y6, Y2
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VPXOR 0(SP), Y7, Y3
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LOAD_MSG_AVX2(SI, 0, 2, 4, 6, 1, 3, 5, 7, 8, 10, 12, 14, 9, 11, 13, 15)
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VMOVDQA Y12, 32(SP)
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VMOVDQA Y13, 64(SP)
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VMOVDQA Y14, 96(SP)
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VMOVDQA Y15, 128(SP)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 14, 4, 9, 13, 10, 8, 15, 6, 1, 0, 11, 5, 12, 2, 7, 3)
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VMOVDQA Y12, 160(SP)
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VMOVDQA Y13, 192(SP)
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VMOVDQA Y14, 224(SP)
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VMOVDQA Y15, 256(SP)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 11, 12, 5, 15, 8, 0, 2, 13, 10, 3, 7, 9, 14, 6, 1, 4)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 7, 3, 13, 11, 9, 1, 12, 14, 2, 5, 4, 15, 6, 10, 0, 8)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 9, 5, 2, 10, 0, 7, 4, 15, 14, 11, 6, 3, 1, 12, 8, 13)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 2, 6, 0, 8, 12, 10, 11, 3, 4, 7, 15, 1, 13, 5, 14, 9)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 12, 1, 14, 4, 5, 15, 13, 10, 0, 6, 9, 8, 7, 3, 2, 11)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 13, 7, 12, 3, 11, 14, 1, 9, 5, 15, 8, 2, 0, 4, 6, 10)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 6, 14, 11, 0, 15, 9, 3, 8, 12, 13, 1, 10, 2, 7, 4, 5)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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LOAD_MSG_AVX2(SI, 10, 8, 7, 1, 2, 4, 6, 5, 15, 9, 3, 13, 11, 14, 12, 0)
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ROUND_AVX2(Y12, Y13, Y14, Y15, Y10, Y4, Y5)
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ROUND_AVX2(32(SP), 64(SP), 96(SP), 128(SP), Y10, Y4, Y5)
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ROUND_AVX2(160(SP), 192(SP), 224(SP), 256(SP), Y10, Y4, Y5)
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VPXOR Y0, Y8, Y8
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VPXOR Y1, Y9, Y9
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VPXOR Y2, Y8, Y8
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VPXOR Y3, Y9, Y9
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LEAQ 128(SI), SI
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SUBQ $128, DI
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JNE loop
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MOVQ R8, 0(BX)
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MOVQ R9, 8(BX)
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VMOVDQU Y8, 0(AX)
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VMOVDQU Y9, 32(AX)
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MOVQ DX, SP
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RET
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// unfortunately the BYTE representation of VPUNPCKLQDQ and VPUNPCKHQDQ must be used
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#define VPUNPCKLQDQ_X8_X8_X10 BYTE $0xC4; BYTE $0x41; BYTE $0x39; BYTE $0x6C; BYTE $0xD0
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#define VPUNPCKHQDQ_X7_X10_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xF2
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#define VPUNPCKLQDQ_X7_X7_X10 BYTE $0xC5; BYTE $0x41; BYTE $0x6C; BYTE $0xD7
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#define VPUNPCKHQDQ_X8_X10_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x39; BYTE $0x6D; BYTE $0xFA
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#define VPUNPCKLQDQ_X3_X3_X10 BYTE $0xC5; BYTE $0x61; BYTE $0x6C; BYTE $0xD3
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#define VPUNPCKHQDQ_X2_X10_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x69; BYTE $0x6D; BYTE $0xD2
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#define VPUNPCKLQDQ_X9_X9_X10 BYTE $0xC4; BYTE $0x41; BYTE $0x31; BYTE $0x6C; BYTE $0xD1
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#define VPUNPCKHQDQ_X3_X10_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xDA
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#define VPUNPCKLQDQ_X2_X2_X10 BYTE $0xC5; BYTE $0x69; BYTE $0x6C; BYTE $0xD2
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#define VPUNPCKHQDQ_X3_X10_X2 BYTE $0xC4; BYTE $0xC1; BYTE $0x61; BYTE $0x6D; BYTE $0xD2
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#define VPUNPCKHQDQ_X8_X10_X3 BYTE $0xC4; BYTE $0xC1; BYTE $0x39; BYTE $0x6D; BYTE $0xDA
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#define VPUNPCKHQDQ_X6_X10_X6 BYTE $0xC4; BYTE $0xC1; BYTE $0x49; BYTE $0x6D; BYTE $0xF2
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#define VPUNPCKHQDQ_X7_X10_X7 BYTE $0xC4; BYTE $0xC1; BYTE $0x41; BYTE $0x6D; BYTE $0xFA
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// shuffle X2 and X6 using the temp registers X8, X9, X10
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#define SHUFFLE_AVX() \
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VMOVDQA X4, X9; \
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VMOVDQA X5, X4; \
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VMOVDQA X9, X5; \
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VMOVDQA X6, X8; \
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VPUNPCKLQDQ_X8_X8_X10; \
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VPUNPCKHQDQ_X7_X10_X6; \
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VPUNPCKLQDQ_X7_X7_X10; \
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VPUNPCKHQDQ_X8_X10_X7; \
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VPUNPCKLQDQ_X3_X3_X10; \
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VMOVDQA X2, X9; \
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VPUNPCKHQDQ_X2_X10_X2; \
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VPUNPCKLQDQ_X9_X9_X10; \
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VPUNPCKHQDQ_X3_X10_X3; \
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// inverse shuffle X2 and X6 using the temp registers X8, X9, X10
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#define SHUFFLE_AVX_INV() \
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VMOVDQA X4, X9; \
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VMOVDQA X5, X4; \
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VMOVDQA X9, X5; \
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VMOVDQA X2, X8; \
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VPUNPCKLQDQ_X2_X2_X10; \
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VPUNPCKHQDQ_X3_X10_X2; \
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VPUNPCKLQDQ_X3_X3_X10; \
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VPUNPCKHQDQ_X8_X10_X3; \
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VPUNPCKLQDQ_X7_X7_X10; \
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VMOVDQA X6, X9; \
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VPUNPCKHQDQ_X6_X10_X6; \
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VPUNPCKLQDQ_X9_X9_X10; \
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VPUNPCKHQDQ_X7_X10_X7; \
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#define HALF_ROUND_AVX(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \
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VPADDQ m0, v0, v0; \
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VPADDQ v2, v0, v0; \
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VPADDQ m1, v1, v1; \
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VPADDQ v3, v1, v1; \
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VPXOR v0, v6, v6; \
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VPXOR v1, v7, v7; \
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VPSHUFD $-79, v6, v6; \
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VPSHUFD $-79, v7, v7; \
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VPADDQ v6, v4, v4; \
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VPADDQ v7, v5, v5; \
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VPXOR v4, v2, v2; \
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VPXOR v5, v3, v3; \
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VPSHUFB c40, v2, v2; \
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VPSHUFB c40, v3, v3; \
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VPADDQ m2, v0, v0; \
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VPADDQ v2, v0, v0; \
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VPADDQ m3, v1, v1; \
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VPADDQ v3, v1, v1; \
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VPXOR v0, v6, v6; \
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VPXOR v1, v7, v7; \
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VPSHUFB c48, v6, v6; \
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VPSHUFB c48, v7, v7; \
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VPADDQ v6, v4, v4; \
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VPADDQ v7, v5, v5; \
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VPXOR v4, v2, v2; \
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VPXOR v5, v3, v3; \
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VPADDQ v2, v2, t0; \
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VPSRLQ $63, v2, v2; \
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VPXOR t0, v2, v2; \
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VPADDQ v3, v3, t0; \
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VPSRLQ $63, v3, v3; \
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VPXOR t0, v3, v3
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// unfortunately the BYTE representation of VPINSRQ must be used
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#define VPINSRQ_1_R10_X8_X8 BYTE $0xC4; BYTE $0x43; BYTE $0xB9; BYTE $0x22; BYTE $0xC2; BYTE $0x01
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#define VPINSRQ_1_R11_X9_X9 BYTE $0xC4; BYTE $0x43; BYTE $0xB1; BYTE $0x22; BYTE $0xCB; BYTE $0x01
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#define VPINSRQ_1_R12_X10_X10 BYTE $0xC4; BYTE $0x43; BYTE $0xA9; BYTE $0x22; BYTE $0xD4; BYTE $0x01
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#define VPINSRQ_1_R13_X11_X11 BYTE $0xC4; BYTE $0x43; BYTE $0xA1; BYTE $0x22; BYTE $0xDD; BYTE $0x01
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#define VPINSRQ_1_R9_X8_X8 BYTE $0xC4; BYTE $0x43; BYTE $0xB9; BYTE $0x22; BYTE $0xC1; BYTE $0x01
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// load src into X8, X9, X10 and X11 using R10, R11, R12 and R13 for temp registers
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#define LOAD_MSG_AVX(src, i0, i1, i2, i3, i4, i5, i6, i7) \
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MOVQ i0*8(src), X8; \
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MOVQ i1*8(src), R10; \
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MOVQ i2*8(src), X9; \
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MOVQ i3*8(src), R11; \
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MOVQ i4*8(src), X10; \
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MOVQ i5*8(src), R12; \
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MOVQ i6*8(src), X11; \
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MOVQ i7*8(src), R13; \
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VPINSRQ_1_R10_X8_X8; \
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VPINSRQ_1_R11_X9_X9; \
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VPINSRQ_1_R12_X10_X10; \
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VPINSRQ_1_R13_X11_X11
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// func hashBlocksAVX(h *[8]uint64, c *[2]uint64, flag uint64, blocks []byte)
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TEXT ·hashBlocksAVX(SB), 4, $288-48 // frame size = 272 + 16 byte alignment
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MOVQ h+0(FP), AX
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MOVQ c+8(FP), BX
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MOVQ flag+16(FP), CX
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MOVQ blocks_base+24(FP), SI
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MOVQ blocks_len+32(FP), DI
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MOVQ SP, BP
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MOVQ SP, R9
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ADDQ $15, R9
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ANDQ $~15, R9
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MOVQ R9, SP
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MOVOU ·AVX_c40<>(SB), X13
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MOVOU ·AVX_c48<>(SB), X14
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VMOVDQU ·AVX_iv3<>(SB), X0
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VMOVDQA X0, 0(SP)
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XORQ CX, 0(SP) // 0(SP) = ·AVX_iv3 ^ (CX || 0)
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VMOVDQU 0(AX), X12
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VMOVDQU 16(AX), X15
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VMOVDQU 32(AX), X2
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VMOVDQU 48(AX), X3
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MOVQ 0(BX), R8
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MOVQ 8(BX), R9
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loop:
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ADDQ $128, R8
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CMPQ R8, $128
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JGE noinc
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INCQ R9
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noinc:
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MOVQ R8, X8
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VPINSRQ_1_R9_X8_X8
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VMOVDQA X12, X0
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VMOVDQA X15, X1
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VMOVDQU ·AVX_iv0<>(SB), X4
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VMOVDQU ·AVX_iv1<>(SB), X5
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VMOVDQU ·AVX_iv2<>(SB), X6
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VPXOR X8, X6, X6
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VMOVDQA 0(SP), X7
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LOAD_MSG_AVX(SI, 0, 2, 4, 6, 1, 3, 5, 7)
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VMOVDQA X8, 16(SP)
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VMOVDQA X9, 32(SP)
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VMOVDQA X10, 48(SP)
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VMOVDQA X11, 64(SP)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 8, 10, 12, 14, 9, 11, 13, 15)
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VMOVDQA X8, 80(SP)
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VMOVDQA X9, 96(SP)
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VMOVDQA X10, 112(SP)
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VMOVDQA X11, 128(SP)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 14, 4, 9, 13, 10, 8, 15, 6)
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VMOVDQA X8, 144(SP)
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VMOVDQA X9, 160(SP)
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VMOVDQA X10, 176(SP)
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VMOVDQA X11, 192(SP)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 1, 0, 11, 5, 12, 2, 7, 3)
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VMOVDQA X8, 208(SP)
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VMOVDQA X9, 224(SP)
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VMOVDQA X10, 240(SP)
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VMOVDQA X11, 256(SP)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 11, 12, 5, 15, 8, 0, 2, 13)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 10, 3, 7, 9, 14, 6, 1, 4)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 7, 3, 13, 11, 9, 1, 12, 14)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 2, 5, 4, 15, 6, 10, 0, 8)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 9, 5, 2, 10, 0, 7, 4, 15)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 14, 11, 6, 3, 1, 12, 8, 13)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 2, 6, 0, 8, 12, 10, 11, 3)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 4, 7, 15, 1, 13, 5, 14, 9)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 12, 1, 14, 4, 5, 15, 13, 10)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 0, 6, 9, 8, 7, 3, 2, 11)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 13, 7, 12, 3, 11, 14, 1, 9)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 5, 15, 8, 2, 0, 4, 6, 10)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 6, 14, 11, 0, 15, 9, 3, 8)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 12, 13, 1, 10, 2, 7, 4, 5)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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LOAD_MSG_AVX(SI, 10, 8, 7, 1, 2, 4, 6, 5)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX()
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LOAD_MSG_AVX(SI, 15, 9, 3, 13, 11, 14, 12, 0)
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_AVX_INV()
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, 16(SP), 32(SP), 48(SP), 64(SP), X11, X13, X14)
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SHUFFLE_AVX()
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, 80(SP), 96(SP), 112(SP), 128(SP), X11, X13, X14)
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SHUFFLE_AVX_INV()
|
|
|
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, 144(SP), 160(SP), 176(SP), 192(SP), X11, X13, X14)
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SHUFFLE_AVX()
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HALF_ROUND_AVX(X0, X1, X2, X3, X4, X5, X6, X7, 208(SP), 224(SP), 240(SP), 256(SP), X11, X13, X14)
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SHUFFLE_AVX_INV()
|
|
|
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VMOVDQU 32(AX), X10
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VMOVDQU 48(AX), X11
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VPXOR X0, X12, X12
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VPXOR X1, X15, X15
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VPXOR X2, X10, X10
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VPXOR X3, X11, X11
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VPXOR X4, X12, X12
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VPXOR X5, X15, X15
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VPXOR X6, X10, X2
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VPXOR X7, X11, X3
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VMOVDQU X2, 32(AX)
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VMOVDQU X3, 48(AX)
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|
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LEAQ 128(SI), SI
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SUBQ $128, DI
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JNE loop
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VMOVDQU X12, 0(AX)
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VMOVDQU X15, 16(AX)
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|
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MOVQ R8, 0(BX)
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MOVQ R9, 8(BX)
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|
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VZEROUPPER
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|
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MOVQ BP, SP
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RET
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// func supportsAVX2() bool
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TEXT ·supportsAVX2(SB), 4, $0-1
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MOVQ runtime·support_avx2(SB), AX
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MOVB AX, ret+0(FP)
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RET
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|
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// func supportsAVX() bool
|
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TEXT ·supportsAVX(SB), 4, $0-1
|
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MOVQ runtime·support_avx(SB), AX
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MOVB AX, ret+0(FP)
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RET
|