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Macroify fwstart.S more

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This commit is contained in:
Vladimir 'phcoder' Serbinenko 2010-04-05 22:39:58 +02:00
parent a6132b9f3f
commit 04a3792f87
3 changed files with 17 additions and 11 deletions
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3
include/grub/mips/loongson.h
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@ -67,6 +67,9 @@
#define GRUB_CPU_LOONGSON_LIOCFG 0xbfe00108
#define GRUB_CPU_LOONGSON_ROM_DELAY_OFFSET 2
#define GRUB_CPU_LOONGSON_ROM_DELAY_MASK 0x1f
#define GRUB_CPU_LOONGSON_CORECFG 0xbfe00180
#define GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE 0x100
#define GRUB_CPU_LOONGSON_CORECFG_BUFFER_CPU 0x200
#define GRUB_CPU_LOONGSON_GPIOCFG 0xbfe00120
#define GRUB_CPU_LOONGSON_SHUTDOWN_GPIO 1

1
include/grub/mips/yeeloong/serial.h
View file

@ -19,6 +19,7 @@
#ifndef GRUB_MACHINE_SERIAL_HEADER
#define GRUB_MACHINE_SERIAL_HEADER 1
#define GRUB_MACHINE_SERIAL_DIVISOR_115200 2
#define GRUB_MACHINE_SERIAL_PORT 0xbff003f8
#ifndef ASM_FILE

24
kern/mips/yeeloong/fwstart.S
View file

@ -116,17 +116,19 @@ __start:
move $a0, $v0
bal read_spd
ori $a0, $zero, 2
ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_ADDR
ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_DDR2
lui $a0, %hi(unimplemented_memory_type)
bne $t0, $v0, fatal
addiu $a0, $a0, %hi(unimplemented_memory_type)
/* And here is our goal: DDR2 controller initialisation. */
lui $t0, 0xbfe0
ld $t1, 0x0180($t0)
andi $t1, $t1, 0x4ff
sd $t1, 0x0180($t0)
lui $t0, %hi(GRUB_CPU_LOONGSON_CORECFG)
ld $t1, %lo(GRUB_CPU_LOONGSON_CORECFG) ($t0)
/* Use addiu for sign-extension. */
addiu $t2, $zero, ~(GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE|GRUB_CPU_LOONGSON_CORECFG_BUFFER_CPU)
and $t1, $t1, $t2
sd $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
b continue
@ -218,7 +220,7 @@ serial_hw_init:
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_LCR)($t0)
/* Set the baud rate 115200. */
ori $t1, $zero, 2
ori $t1, $zero, GRUB_MACHINE_SERIAL_DIVISOR_115200
sb $t1, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_DLL)($t0)
sb $zero, (%lo (GRUB_MACHINE_SERIAL_PORT) + UART_DLH)($t0)
@ -430,7 +432,7 @@ regdump:
write_dumpreg:
ld $t2, 0($t6)
sd $t2, 0($t4)
addiu $t4, $t4, 0x10
addiu $t4, $t4, GRUB_MACHINE_DDR2_REG_STEP
jr $ra
addiu $t6, $t6, GRUB_MACHINE_DDR2_REG_SIZE
@ -531,10 +533,10 @@ continue:
sd $t5, (%lo(GRUB_MACHINE_DDR2_BASE) + 0x30) ($t4)
/* Desactivate DDR2 registers. */
lui $t0, 0xbfe0
ld $t1, 0x0180($t0)
ori $t1, $t1, 0x100
sd $t1, 0x0180($t0)
lui $t0, %hi (GRUB_CPU_LOONGSON_CORECFG)
ld $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
ori $t1, $t1, GRUB_CPU_LOONGSON_CORECFG_DISABLE_DDR2_SPACE
sd $t1, %lo (GRUB_CPU_LOONGSON_CORECFG) ($t0)
/* Enable cache. */
mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG