ehci: Split core code from PCI part.
On ARM often EHCI is present without PCI and just declared in device tree. So splitcore from PCI part.
This commit is contained in:
Vladimir Serbinenko
parent
265292f2b0
commit
058df7b5a9
3 changed files with 223 additions and 187 deletions
208
grub-core/bus/usb/ehci-pci.c
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208
grub-core/bus/usb/ehci-pci.c
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/* ehci.c - EHCI Support. */
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/*
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* GRUB -- GRand Unified Bootloader
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* Copyright (C) 2011 Free Software Foundation, Inc.
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*
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* GRUB is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GRUB is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <grub/pci.h>
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#include <grub/cpu/pci.h>
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#include <grub/cs5536.h>
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#include <grub/misc.h>
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#include <grub/mm.h>
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#include <grub/time.h>
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#include <grub/usb.h>
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#define GRUB_EHCI_PCI_SBRN_REG 0x60
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#define GRUB_EHCI_ADDR_MEM_MASK (~0xff)
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/* USBLEGSUP bits and related OS OWNED byte offset */
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enum
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{
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GRUB_EHCI_BIOS_OWNED = (1 << 16),
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GRUB_EHCI_OS_OWNED = (1 << 24)
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};
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/* PCI iteration function... */
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static int
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grub_ehci_pci_iter (grub_pci_device_t dev, grub_pci_id_t pciid,
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void *data __attribute__ ((unused)))
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{
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volatile grub_uint32_t *regs;
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grub_uint32_t base, base_h;
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grub_uint32_t eecp_offset;
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grub_uint32_t usblegsup = 0;
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grub_uint64_t maxtime;
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grub_uint32_t interf;
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grub_uint32_t subclass;
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grub_uint32_t class;
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grub_uint8_t release;
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grub_uint32_t class_code;
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grub_dprintf ("ehci", "EHCI grub_ehci_pci_iter: begin\n");
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if (pciid == GRUB_CS5536_PCIID)
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{
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grub_uint64_t basereg;
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basereg = grub_cs5536_read_msr (dev, GRUB_CS5536_MSR_USB_EHCI_BASE);
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if (!(basereg & GRUB_CS5536_MSR_USB_BASE_MEMORY_ENABLE))
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{
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/* Shouldn't happen. */
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grub_dprintf ("ehci", "No EHCI address is assigned\n");
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return 0;
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}
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base = (basereg & GRUB_CS5536_MSR_USB_BASE_ADDR_MASK);
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basereg |= GRUB_CS5536_MSR_USB_BASE_BUS_MASTER;
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basereg &= ~GRUB_CS5536_MSR_USB_BASE_PME_ENABLED;
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basereg &= ~GRUB_CS5536_MSR_USB_BASE_PME_STATUS;
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basereg &= ~GRUB_CS5536_MSR_USB_BASE_SMI_ENABLE;
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grub_cs5536_write_msr (dev, GRUB_CS5536_MSR_USB_EHCI_BASE, basereg);
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}
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else
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{
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grub_pci_address_t addr;
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addr = grub_pci_make_address (dev, GRUB_PCI_REG_CLASS);
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class_code = grub_pci_read (addr) >> 8;
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interf = class_code & 0xFF;
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subclass = (class_code >> 8) & 0xFF;
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class = class_code >> 16;
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/* If this is not an EHCI controller, just return. */
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if (class != 0x0c || subclass != 0x03 || interf != 0x20)
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return 0;
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grub_dprintf ("ehci", "EHCI grub_ehci_pci_iter: class OK\n");
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/* Check Serial Bus Release Number */
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addr = grub_pci_make_address (dev, GRUB_EHCI_PCI_SBRN_REG);
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release = grub_pci_read_byte (addr);
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if (release != 0x20)
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{
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grub_dprintf ("ehci", "EHCI grub_ehci_pci_iter: Wrong SBRN: %0x\n",
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release);
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return 0;
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}
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grub_dprintf ("ehci", "EHCI grub_ehci_pci_iter: bus rev. num. OK\n");
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/* Determine EHCI EHCC registers base address. */
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addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0);
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base = grub_pci_read (addr);
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addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG1);
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base_h = grub_pci_read (addr);
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/* Stop if registers are mapped above 4G - GRUB does not currently
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* work with registers mapped above 4G */
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if (((base & GRUB_PCI_ADDR_MEM_TYPE_MASK) != GRUB_PCI_ADDR_MEM_TYPE_32)
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&& (base_h != 0))
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{
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grub_dprintf ("ehci",
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"EHCI grub_ehci_pci_iter: registers above 4G are not supported\n");
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return 0;
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}
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base &= GRUB_PCI_ADDR_MEM_MASK;
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if (!base)
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{
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grub_dprintf ("ehci",
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"EHCI: EHCI is not mapped\n");
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return 0;
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}
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/* Set bus master - needed for coreboot, VMware, broken BIOSes etc. */
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addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND);
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grub_pci_write_word(addr,
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GRUB_PCI_COMMAND_MEM_ENABLED
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| GRUB_PCI_COMMAND_BUS_MASTER
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| grub_pci_read_word(addr));
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grub_dprintf ("ehci", "EHCI grub_ehci_pci_iter: 32-bit EHCI OK\n");
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}
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grub_dprintf ("ehci", "EHCI grub_ehci_pci_iter: iobase of EHCC: %08x\n",
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(base & GRUB_EHCI_ADDR_MEM_MASK));
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regs = grub_pci_device_map_range (dev,
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(base & GRUB_EHCI_ADDR_MEM_MASK),
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0x100);
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/* Is there EECP ? */
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eecp_offset = (grub_le_to_cpu32 (regs[2]) >> 8) & 0xff;
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/* Determine and change ownership. */
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/* EECP offset valid in HCCPARAMS */
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/* Ownership can be changed via EECP only */
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if (pciid != GRUB_CS5536_PCIID && eecp_offset >= 0x40)
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{
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grub_pci_address_t pciaddr_eecp;
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pciaddr_eecp = grub_pci_make_address (dev, eecp_offset);
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usblegsup = grub_pci_read (pciaddr_eecp);
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if (usblegsup & GRUB_EHCI_BIOS_OWNED)
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{
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grub_boot_time ("Taking ownership of EHCI controller");
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grub_dprintf ("ehci",
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"EHCI grub_ehci_pci_iter: EHCI owned by: BIOS\n");
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/* Ownership change - set OS_OWNED bit */
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grub_pci_write (pciaddr_eecp, usblegsup | GRUB_EHCI_OS_OWNED);
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/* Ensure PCI register is written */
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grub_pci_read (pciaddr_eecp);
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/* Wait for finish of ownership change, EHCI specification
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* doesn't say how long it can take... */
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maxtime = grub_get_time_ms () + 1000;
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while ((grub_pci_read (pciaddr_eecp) & GRUB_EHCI_BIOS_OWNED)
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&& (grub_get_time_ms () < maxtime));
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if (grub_pci_read (pciaddr_eecp) & GRUB_EHCI_BIOS_OWNED)
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{
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grub_dprintf ("ehci",
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"EHCI grub_ehci_pci_iter: EHCI change ownership timeout");
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/* Change ownership in "hard way" - reset BIOS ownership */
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grub_pci_write (pciaddr_eecp, GRUB_EHCI_OS_OWNED);
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/* Ensure PCI register is written */
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grub_pci_read (pciaddr_eecp);
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}
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}
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else if (usblegsup & GRUB_EHCI_OS_OWNED)
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/* XXX: What to do in this case - nothing ? Can it happen ? */
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grub_dprintf ("ehci", "EHCI grub_ehci_pci_iter: EHCI owned by: OS\n");
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else
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{
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grub_dprintf ("ehci",
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"EHCI grub_ehci_pci_iter: EHCI owned by: NONE\n");
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/* XXX: What to do in this case ? Can it happen ?
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* Is code below correct ? */
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/* Ownership change - set OS_OWNED bit */
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grub_pci_write (pciaddr_eecp, GRUB_EHCI_OS_OWNED);
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/* Ensure PCI register is written */
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grub_pci_read (pciaddr_eecp);
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}
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/* Disable SMI, just to be sure. */
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pciaddr_eecp = grub_pci_make_address (dev, eecp_offset + 4);
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grub_pci_write (pciaddr_eecp, 0);
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/* Ensure PCI register is written */
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grub_pci_read (pciaddr_eecp);
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}
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grub_dprintf ("ehci", "inithw: EHCI grub_ehci_pci_iter: ownership OK\n");
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grub_ehci_init_device (regs);
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return 0;
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}
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void
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grub_ehci_pci_scan (void)
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{
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grub_pci_iterate (grub_ehci_pci_iter, NULL);
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}
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