Remove -march=mips3 from TARGET_CCASFLAGS as it creates linking problem
when rest of GRUB is compiled for hisher stepping. Instead use .set mips3/.set mips1 around cache and sync opcodes.
This commit is contained in:
parent
4906052019
commit
0d8f04cd83
4 changed files with 38 additions and 19 deletions
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@ -1,3 +1,9 @@
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2013-11-22 Vladimir Serbinenko <phcoder@gmail.com>
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Remove -march=mips3 from TARGET_CCASFLAGS as it creates linking problem
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when rest of GRUB is compiled for hisher stepping. Instead use
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.set mips3/.set mips1 around cache and sync opcodes.
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2013-11-21 Vladimir Serbinenko <phcoder@gmail.com>
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2013-11-21 Vladimir Serbinenko <phcoder@gmail.com>
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Unify GOT/trampoline handling between PPC, MIPS and IA64 as they
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Unify GOT/trampoline handling between PPC, MIPS and IA64 as they
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@ -12,7 +12,6 @@ if COND_mips_loongson
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endif
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endif
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if COND_mips
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if COND_mips
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CFLAGS_PLATFORM += -mflush-func=grub_red_herring
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CFLAGS_PLATFORM += -mflush-func=grub_red_herring
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CCASFLAGS_PLATFORM = -march=mips3
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endif
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endif
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if COND_sparc64_ieee1275
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if COND_sparc64_ieee1275
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CFLAGS_PLATFORM += -mno-app-regs
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CFLAGS_PLATFORM += -mno-app-regs
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@ -20,11 +20,11 @@ FUNCTION (grub_arch_sync_dma_caches)
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move $t0, $t2
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move $t0, $t2
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subu $t1, $t3, $t2
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subu $t1, $t3, $t2
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1:
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1:
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cache 1, 0($t0)
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cache_op 1, 0($t0)
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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cache 1, 1($t0)
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cache_op 1, 1($t0)
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cache 1, 2($t0)
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cache_op 1, 2($t0)
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cache 1, 3($t0)
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cache_op 1, 3($t0)
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addiu $t1, $t1, -0x20
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addiu $t1, $t1, -0x20
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bne $t1, $zero, 1b
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bne $t1, $zero, 1b
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@ -34,36 +34,36 @@ FUNCTION (grub_arch_sync_dma_caches)
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bne $t1, $zero, 1b
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bne $t1, $zero, 1b
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addiu $t0, $t0, 0x4
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addiu $t0, $t0, 0x4
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#endif
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#endif
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sync
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sync_op
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move $t0, $t2
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move $t0, $t2
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subu $t1, $t3, $t2
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subu $t1, $t3, $t2
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2:
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2:
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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cache 0, 0($t0)
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cache_op 0, 0($t0)
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addiu $t1, $t1, -0x20
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addiu $t1, $t1, -0x20
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bne $t1, $zero, 2b
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bne $t1, $zero, 2b
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addiu $t0, $t0, 0x20
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addiu $t0, $t0, 0x20
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#else
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#else
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cache 0, 0($t0)
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cache_op 0, 0($t0)
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addiu $t1, $t1, -4
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addiu $t1, $t1, -4
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bne $t1, $zero, 2b
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bne $t1, $zero, 2b
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addiu $t0, $t0, 0x4
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addiu $t0, $t0, 0x4
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#endif
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#endif
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sync
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sync_op
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move $t0, $t2
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move $t0, $t2
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subu $t1, $t3, $t2
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subu $t1, $t3, $t2
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2:
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2:
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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cache 23, 0($t0)
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cache_op 23, 0($t0)
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addiu $t1, $t1, -0x20
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addiu $t1, $t1, -0x20
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bne $t1, $zero, 2b
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bne $t1, $zero, 2b
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addiu $t0, $t0, 0x20
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addiu $t0, $t0, 0x20
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#else
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#else
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cache 23, 0($t0)
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cache_op 23, 0($t0)
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addiu $t1, $t1, -0x4
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addiu $t1, $t1, -0x4
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bne $t1, $zero, 2b
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bne $t1, $zero, 2b
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addiu $t0, $t0, 0x4
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addiu $t0, $t0, 0x4
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#endif
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#endif
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sync
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sync_op
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jr $ra
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jr $ra
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@ -1,3 +1,17 @@
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#ifndef CACHE_OP_DEFINED
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#define CACHE_OP_DEFINED 1
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.macro cache_op op addr
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.set mips3
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cache \op, \addr
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.set mips1
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.endm
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.macro sync_op
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.set mips3
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sync
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.set mips1
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.endm
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#endif
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move $t2, $a0
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move $t2, $a0
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addu $t3, $a0, $a1
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addu $t3, $a0, $a1
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srl $t2, $t2, 5
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srl $t2, $t2, 5
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@ -8,12 +22,12 @@
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move $t0, $t2
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move $t0, $t2
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subu $t1, $t3, $t2
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subu $t1, $t3, $t2
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1:
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1:
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cache 1, 0($t0)
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cache_op 1, 0($t0)
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/* All four ways. */
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/* All four ways. */
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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cache 1, 1($t0)
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cache_op 1, 1($t0)
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cache 1, 2($t0)
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cache_op 1, 2($t0)
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cache 1, 3($t0)
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cache_op 1, 3($t0)
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addiu $t1, $t1, -0x20
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addiu $t1, $t1, -0x20
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bne $t1, $zero, 1b
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bne $t1, $zero, 1b
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addiu $t0, $t0, 0x20
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addiu $t0, $t0, 0x20
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@ -23,11 +37,11 @@
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bne $t1, $zero, 1b
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bne $t1, $zero, 1b
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addiu $t0, $t0, 0x4
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addiu $t0, $t0, 0x4
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#endif
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#endif
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sync
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sync_op
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move $t0, $t2
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move $t0, $t2
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subu $t1, $t3, $t2
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subu $t1, $t3, $t2
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2:
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2:
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cache 0, 0($t0)
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cache_op 0, 0($t0)
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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#ifdef GRUB_MACHINE_MIPS_LOONGSON
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addiu $t1, $t1, -0x20
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addiu $t1, $t1, -0x20
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bne $t1, $zero, 2b
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bne $t1, $zero, 2b
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@ -37,4 +51,4 @@
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bne $t1, $zero, 2b
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bne $t1, $zero, 2b
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addiu $t0, $t0, 0x4
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addiu $t0, $t0, 0x4
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#endif
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#endif
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sync
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sync_op
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