Remove -march=mips3 from TARGET_CCASFLAGS as it creates linking problem

when rest of GRUB is compiled for hisher stepping. Instead use
	.set mips3/.set mips1 around cache and sync opcodes.
This commit is contained in:
Vladimir Serbinenko 2013-11-22 04:36:53 +01:00
parent 4906052019
commit 0d8f04cd83
4 changed files with 38 additions and 19 deletions

View file

@ -1,3 +1,9 @@
2013-11-22 Vladimir Serbinenko <phcoder@gmail.com>
Remove -march=mips3 from TARGET_CCASFLAGS as it creates linking problem
when rest of GRUB is compiled for hisher stepping. Instead use
.set mips3/.set mips1 around cache and sync opcodes.
2013-11-21 Vladimir Serbinenko <phcoder@gmail.com> 2013-11-21 Vladimir Serbinenko <phcoder@gmail.com>
Unify GOT/trampoline handling between PPC, MIPS and IA64 as they Unify GOT/trampoline handling between PPC, MIPS and IA64 as they

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@ -12,7 +12,6 @@ if COND_mips_loongson
endif endif
if COND_mips if COND_mips
CFLAGS_PLATFORM += -mflush-func=grub_red_herring CFLAGS_PLATFORM += -mflush-func=grub_red_herring
CCASFLAGS_PLATFORM = -march=mips3
endif endif
if COND_sparc64_ieee1275 if COND_sparc64_ieee1275
CFLAGS_PLATFORM += -mno-app-regs CFLAGS_PLATFORM += -mno-app-regs

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@ -20,11 +20,11 @@ FUNCTION (grub_arch_sync_dma_caches)
move $t0, $t2 move $t0, $t2
subu $t1, $t3, $t2 subu $t1, $t3, $t2
1: 1:
cache 1, 0($t0) cache_op 1, 0($t0)
#ifdef GRUB_MACHINE_MIPS_LOONGSON #ifdef GRUB_MACHINE_MIPS_LOONGSON
cache 1, 1($t0) cache_op 1, 1($t0)
cache 1, 2($t0) cache_op 1, 2($t0)
cache 1, 3($t0) cache_op 1, 3($t0)
addiu $t1, $t1, -0x20 addiu $t1, $t1, -0x20
bne $t1, $zero, 1b bne $t1, $zero, 1b
@ -34,36 +34,36 @@ FUNCTION (grub_arch_sync_dma_caches)
bne $t1, $zero, 1b bne $t1, $zero, 1b
addiu $t0, $t0, 0x4 addiu $t0, $t0, 0x4
#endif #endif
sync sync_op
move $t0, $t2 move $t0, $t2
subu $t1, $t3, $t2 subu $t1, $t3, $t2
2: 2:
#ifdef GRUB_MACHINE_MIPS_LOONGSON #ifdef GRUB_MACHINE_MIPS_LOONGSON
cache 0, 0($t0) cache_op 0, 0($t0)
addiu $t1, $t1, -0x20 addiu $t1, $t1, -0x20
bne $t1, $zero, 2b bne $t1, $zero, 2b
addiu $t0, $t0, 0x20 addiu $t0, $t0, 0x20
#else #else
cache 0, 0($t0) cache_op 0, 0($t0)
addiu $t1, $t1, -4 addiu $t1, $t1, -4
bne $t1, $zero, 2b bne $t1, $zero, 2b
addiu $t0, $t0, 0x4 addiu $t0, $t0, 0x4
#endif #endif
sync sync_op
move $t0, $t2 move $t0, $t2
subu $t1, $t3, $t2 subu $t1, $t3, $t2
2: 2:
#ifdef GRUB_MACHINE_MIPS_LOONGSON #ifdef GRUB_MACHINE_MIPS_LOONGSON
cache 23, 0($t0) cache_op 23, 0($t0)
addiu $t1, $t1, -0x20 addiu $t1, $t1, -0x20
bne $t1, $zero, 2b bne $t1, $zero, 2b
addiu $t0, $t0, 0x20 addiu $t0, $t0, 0x20
#else #else
cache 23, 0($t0) cache_op 23, 0($t0)
addiu $t1, $t1, -0x4 addiu $t1, $t1, -0x4
bne $t1, $zero, 2b bne $t1, $zero, 2b
addiu $t0, $t0, 0x4 addiu $t0, $t0, 0x4
#endif #endif
sync sync_op
jr $ra jr $ra

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@ -1,3 +1,17 @@
#ifndef CACHE_OP_DEFINED
#define CACHE_OP_DEFINED 1
.macro cache_op op addr
.set mips3
cache \op, \addr
.set mips1
.endm
.macro sync_op
.set mips3
sync
.set mips1
.endm
#endif
move $t2, $a0 move $t2, $a0
addu $t3, $a0, $a1 addu $t3, $a0, $a1
srl $t2, $t2, 5 srl $t2, $t2, 5
@ -8,12 +22,12 @@
move $t0, $t2 move $t0, $t2
subu $t1, $t3, $t2 subu $t1, $t3, $t2
1: 1:
cache 1, 0($t0) cache_op 1, 0($t0)
/* All four ways. */ /* All four ways. */
#ifdef GRUB_MACHINE_MIPS_LOONGSON #ifdef GRUB_MACHINE_MIPS_LOONGSON
cache 1, 1($t0) cache_op 1, 1($t0)
cache 1, 2($t0) cache_op 1, 2($t0)
cache 1, 3($t0) cache_op 1, 3($t0)
addiu $t1, $t1, -0x20 addiu $t1, $t1, -0x20
bne $t1, $zero, 1b bne $t1, $zero, 1b
addiu $t0, $t0, 0x20 addiu $t0, $t0, 0x20
@ -23,11 +37,11 @@
bne $t1, $zero, 1b bne $t1, $zero, 1b
addiu $t0, $t0, 0x4 addiu $t0, $t0, 0x4
#endif #endif
sync sync_op
move $t0, $t2 move $t0, $t2
subu $t1, $t3, $t2 subu $t1, $t3, $t2
2: 2:
cache 0, 0($t0) cache_op 0, 0($t0)
#ifdef GRUB_MACHINE_MIPS_LOONGSON #ifdef GRUB_MACHINE_MIPS_LOONGSON
addiu $t1, $t1, -0x20 addiu $t1, $t1, -0x20
bne $t1, $zero, 2b bne $t1, $zero, 2b
@ -37,4 +51,4 @@
bne $t1, $zero, 2b bne $t1, $zero, 2b
addiu $t0, $t0, 0x4 addiu $t0, $t0, 0x4
#endif #endif
sync sync_op