Detect cache type on runtime rather than compile time
This commit is contained in:
Vladimir 'phcoder' Serbinenko
parent
c59fe1d776
commit
390df92f0b
5 changed files with 238 additions and 148 deletions
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@ -22,16 +22,7 @@
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.text
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.syntax unified
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.arm
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#if (__ARM_ARCH_6__ == 1)
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.arch armv6
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# define DMB mcr p15, 0, r0, c7, c10, 5
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# define DSB mcr p15, 0, r0, c7, c10, 4
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# define ISB mcr p15, 0, r0, c7, c5, 4
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#elif (__ARM_ARCH_7A__ == 1)
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# define DMB dmb
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# define DSB dsb
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# define ISB isb
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#else
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#if !defined (ARMV6) && !defined (ARMV7)
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# error Unsupported architecture version!
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#endif
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@ -45,13 +36,13 @@
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@ r1 - *end (exclusive)
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clean_dcache_range:
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@ Clean data cache for range to point-of-unification
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ldr r2, dlinesz
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ldr r2, =EXT_C(grub_arch_cache_dlinesz)
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sub r3, r2, #1 @ align "beg" to start of line
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mvn r3, r3
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and r0, r0, r3
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1: cmp r0, r1
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bge 2f
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#if (__ARM_ARCH_6__ == 1)
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#ifdef ARMV6
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mcr p15, 0, r0, c7, c10, 1 @ Clean data cache line by MVA
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#else
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mcr p15, 0, r0, c7, c11, 1 @ DCCMVAU
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@ -65,7 +56,7 @@ clean_dcache_range:
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@ r1 - *end (exclusive)
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invalidate_icache_range:
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@ Invalidate instruction cache for range to point-of-unification
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ldr r2, ilinesz
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ldr r2, =EXT_C(grub_arch_cache_ilinesz)
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sub r3, r2, #1 @ align "beg" to start of line
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mvn r3, r3
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and r0, r0, r3
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@ -80,151 +71,27 @@ invalidate_icache_range:
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ISB
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bx lr
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sync_caches:
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@void grub_arch_sync_caches (void *address, grub_size_t len)
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#ifdef ARMV6
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FUNCTION(grub_arch_sync_caches_armv6)
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#else
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FUNCTION(grub_arch_sync_caches_armv7)
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#endif
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add r1, r0, r1
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DSB
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push {r0-r1, r4-r6, lr}
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ldr r2, probed @ If first call, probe cache sizes
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cmp r2, #0
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bleq probe_caches
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ldrdeq r0, r1, [sp]
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bl clean_dcache_range
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pop {r0, r1}
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bl invalidate_icache_range
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pop {r4-r6, pc}
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probe_caches:
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push {r4-r6, lr}
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mrc p15, 0, r0, c0, c0, 1 @ Read Cache Type Register
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mov r1, #1
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@ Cache Type Register format changed in ARMv7
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@ r5 - dlinesz
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@ r6 - ilinesz
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#if (__ARM_ARCH_6__ == 1)
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lsl r2, r0, #12
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and r2, r2, #3 @ Dsize 'len'
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lsl r2, r1, r2 @ Convert to num 8-byte blocks
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lsl r5, r2, #3 @ Convert to num bytes
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and r2, r0, #3 @ Isize 'len'
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lsl r2, r1, r2 @ Convert to num 8-byte blocks
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lsl r6, r2, #3 @ Convert to num bytes
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#ifdef ARMV6
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FUNCTION(grub_arm_disable_caches_mmu_armv6)
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#else
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lsr r2, r0, #16 @ Extract min D-cache num word log2
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and r2, r2, #0xf
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add r2, r2, #2 @ words->bytes
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lsl r5, r1, r2 @ Convert to num bytes
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and r2, r0, #0xf @ Extract min I-cache num word log2
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add r2, r2, #2 @ words->bytes
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lsl r6, r1, r2 @ Convert to num bytes
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#endif
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ldr r3, =dlinesz
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str r5, [r3]
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ldr r3, =ilinesz
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str r6, [r3]
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ldr r3, =probed @ Flag cache probing done
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str r1, [r3]
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pop {r4-r6, pc}
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.align 3
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probed: .long 0
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dlinesz:
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.long 0
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ilinesz:
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.long 0
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@void grub_arch_sync_caches (void *address, grub_size_t len)
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FUNCTION(grub_arch_sync_caches)
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add r1, r0, r1
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b sync_caches
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@ r0 - CLIDR
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@ r1 - LoC
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@ r2 - current level
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@ r3 - num sets
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@ r4 - num ways
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@ r5 - current set
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@ r6 - current way
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@ r7 - line size
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@ r8 - scratch
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@ r9 - scratch
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@ r10 - scratch
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@ r11 - scratch
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clean_invalidate_dcache:
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#if (__ARM_ARCH_6__ == 1)
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mcr p15, 0, r0, c7, c14, 0 @ Clean/Invalidate D-cache
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bx lr
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#elif (__ARM_ARCH_7A__ == 1)
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push {r4-r12, lr}
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mrc p15, 1, r0, c0, c0, 1 @ Read CLIDR
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lsr r1, r0, #24 @ Extract LoC
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and r1, r1, #0x7
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mov r2, #0 @ First level, L1
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2: and r8, r0, #7 @ cache type at current level
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cmp r8, #2
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blt 5f @ instruction only, or none, skip level
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@ set current cache level/type (for CCSIDR read)
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lsl r8, r2, #1
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mcr p15, 2, r8, c0, c0, 0 @ Write CSSELR (level, type: data/uni)
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@ read current cache information
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mrc p15, 1, r8, c0, c0, 0 @ Read CCSIDR
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lsr r3, r8, #13 @ Number of sets -1
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ldr r9, =0x3fff
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and r3, r3, r9
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lsr r4, r8, #3 @ Number of ways -1
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ldr r9, =0x1ff
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and r4, r4, r9
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and r7, r8, #7 @ log2(line size in words) - 2
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add r7, r7, #2 @ adjust
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mov r8, #1
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lsl r7, r8, r7 @ -> line size in words
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lsl r7, r7, #2 @ -> bytes
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@ set loop
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mov r5, #0 @ current set = 0
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3: lsl r8, r2, #1 @ insert level
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clz r9, r7 @ calculate set field offset
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mov r10, #31
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sub r9, r10, r9
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lsl r10, r5, r9
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orr r8, r8, r10 @ insert set field
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@ way loop
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@ calculate way field offset
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mov r6, #0 @ current way = 0
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add r10, r4, #1
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clz r9, r10 @ r9 = way field offset
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add r9, r9, #1
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4: lsl r10, r6, r9
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orr r11, r8, r10 @ insert way field
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@ clean and invalidate line by set/way
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mcr p15, 0, r11, c7, c14, 2 @ DCCISW
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@ next way
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add r6, r6, #1
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cmp r6, r4
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ble 4b
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@ next set
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add r5, r5, #1
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cmp r5, r3
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ble 3b
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@ next level
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5: lsr r0, r0, #3 @ align next level CLIDR 'type' field
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add r2, r2, #1 @ increment cache level counter
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cmp r2, r1
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blt 2b @ outer loop
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@ return
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6: DSB
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ISB
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pop {r4-r12, pc}
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FUNCTION(grub_arm_disable_caches_mmu_armv7)
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#endif
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FUNCTION(grub_arm_disable_caches_mmu)
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push {r4, lr}
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@ disable D-cache
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