Replace #define with enum
This commit is contained in:
Vladimir 'phcoder' Serbinenko
parent
2f82ea948d
commit
679cbb4020
1 changed files with 173 additions and 128 deletions
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@ -39,11 +39,14 @@ GRUB_MOD_LICENSE ("GPLv3+");
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#define GRUB_EHCI_PCI_SBRN_REG 0x60
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/* Capability registers offsets */
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#define GRUB_EHCI_EHCC_CAPLEN 0x00 /* byte */
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#define GRUB_EHCI_EHCC_VERSION 0x02 /* word */
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#define GRUB_EHCI_EHCC_SPARAMS 0x04 /* dword */
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#define GRUB_EHCI_EHCC_CPARAMS 0x08 /* dword */
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#define GRUB_EHCI_EHCC_PROUTE 0x0c /* 60 bits */
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enum
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{
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GRUB_EHCI_EHCC_CAPLEN = 0x00, /* byte */
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GRUB_EHCI_EHCC_VERSION = 0x02, /* word */
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GRUB_EHCI_EHCC_SPARAMS = 0x04, /* dword */
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GRUB_EHCI_EHCC_CPARAMS = 0x08, /* dword */
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GRUB_EHCI_EHCC_PROUTE = 0x0c, /* 60 bits */
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};
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#define GRUB_EHCI_EECP_MASK (0xff << 8)
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#define GRUB_EHCI_EECP_SHIFT 8
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@ -52,20 +55,26 @@ GRUB_MOD_LICENSE ("GPLv3+");
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#define GRUB_EHCI_POINTER_MASK (~0x1f)
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/* Capability register SPARAMS bits */
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#define GRUB_EHCI_SPARAMS_N_PORTS (0xf <<0)
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#define GRUB_EHCI_SPARAMS_PPC (1<<4) /* Power port control */
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#define GRUB_EHCI_SPARAMS_PRR (1<<7) /* Port routing rules */
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#define GRUB_EHCI_SPARAMS_N_PCC (0xf<<8) /* No of ports per comp. */
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#define GRUB_EHCI_SPARAMS_NCC (0xf<<12) /* No of com. controllers */
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#define GRUB_EHCI_SPARAMS_P_IND (1<<16) /* Port indicators present */
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#define GRUB_EHCI_SPARAMS_DEBUG_P (0xf<<20) /* Debug port */
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enum
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{
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GRUB_EHCI_SPARAMS_N_PORTS = (0xf << 0),
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GRUB_EHCI_SPARAMS_PPC = (1 << 4), /* Power port control */
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GRUB_EHCI_SPARAMS_PRR = (1 << 7), /* Port routing rules */
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GRUB_EHCI_SPARAMS_N_PCC = (0xf << 8), /* No of ports per comp. */
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GRUB_EHCI_SPARAMS_NCC = (0xf << 12), /* No of com. controllers */
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GRUB_EHCI_SPARAMS_P_IND = (1 << 16), /* Port indicators present */
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GRUB_EHCI_SPARAMS_DEBUG_P = (0xf << 20) /* Debug port */
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};
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#define GRUB_EHCI_MAX_N_PORTS 15 /* Max. number of ports */
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/* Capability register CPARAMS bits */
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#define GRUB_EHCI_CPARAMS_64BIT (1<<0)
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#define GRUB_EHCI_CPARAMS_PROG_FRAMELIST (1<<1)
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#define GRUB_EHCI_CPARAMS_PARK_CAP (1<<2)
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enum
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{
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GRUB_EHCI_CPARAMS_64BIT = (1 << 0),
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GRUB_EHCI_CPARAMS_PROG_FRAMELIST = (1 << 1),
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GRUB_EHCI_CPARAMS_PARK_CAP = (1 << 2)
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};
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#define GRUB_EHCI_N_FRAMELIST 1024
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#define GRUB_EHCI_N_QH 256
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@ -74,137 +83,177 @@ GRUB_MOD_LICENSE ("GPLv3+");
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#define GRUB_EHCI_QH_EMPTY 1
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/* USBLEGSUP bits and related OS OWNED byte offset */
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#define GRUB_EHCI_BIOS_OWNED (1<<16)
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#define GRUB_EHCI_OS_OWNED (1<<24)
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enum
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{
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GRUB_EHCI_BIOS_OWNED = (1 << 16),
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GRUB_EHCI_OS_OWNED = (1 << 24)
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};
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/* Operational registers offsets */
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#define GRUB_EHCI_COMMAND 0x00
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#define GRUB_EHCI_STATUS 0x04
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#define GRUB_EHCI_INTERRUPT 0x08
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#define GRUB_EHCI_FRAME_INDEX 0x0c
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#define GRUB_EHCI_64BIT_SEL 0x10
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#define GRUB_EHCI_FL_BASE 0x14
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#define GRUB_EHCI_CUR_AL_ADDR 0x18
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#define GRUB_EHCI_CONFIG_FLAG 0x40
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#define GRUB_EHCI_PORT_STAT_CMD 0x44
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enum
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{
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GRUB_EHCI_COMMAND = 0x00,
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GRUB_EHCI_STATUS = 0x04,
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GRUB_EHCI_INTERRUPT = 0x08,
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GRUB_EHCI_FRAME_INDEX = 0x0c,
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GRUB_EHCI_64BIT_SEL = 0x10,
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GRUB_EHCI_FL_BASE = 0x14,
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GRUB_EHCI_CUR_AL_ADDR = 0x18,
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GRUB_EHCI_CONFIG_FLAG = 0x40,
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GRUB_EHCI_PORT_STAT_CMD = 0x44
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};
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/* Operational register COMMAND bits */
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#define GRUB_EHCI_CMD_RUNSTOP (1<<0)
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#define GRUB_EHCI_CMD_HC_RESET (1<<1)
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#define GRUB_EHCI_CMD_FL_SIZE (3<<2)
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#define GRUB_EHCI_CMD_PS_ENABL (1<<4)
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#define GRUB_EHCI_CMD_AS_ENABL (1<<5)
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#define GRUB_EHCI_CMD_AS_ADV_D (1<<6)
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#define GRUB_EHCI_CMD_L_HC_RES (1<<7)
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#define GRUB_EHCI_CMD_AS_PARKM (3<<8)
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#define GRUB_EHCI_CMD_AS_PARKE (1<<11)
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#define GRUB_EHCI_CMD_INT_THRS (0xff<<16)
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enum
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{
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GRUB_EHCI_CMD_RUNSTOP = (1 << 0),
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GRUB_EHCI_CMD_HC_RESET = (1 << 1),
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GRUB_EHCI_CMD_FL_SIZE = (3 << 2),
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GRUB_EHCI_CMD_PS_ENABL = (1 << 4),
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GRUB_EHCI_CMD_AS_ENABL = (1 << 5),
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GRUB_EHCI_CMD_AS_ADV_D = (1 << 6),
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GRUB_EHCI_CMD_L_HC_RES = (1 << 7),
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GRUB_EHCI_CMD_AS_PARKM = (3 << 8),
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GRUB_EHCI_CMD_AS_PARKE = (1 << 11),
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GRUB_EHCI_CMD_INT_THRS = (0xff << 16)
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};
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/* Operational register STATUS bits */
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#define GRUB_EHCI_ST_INTERRUPT (1<<0)
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#define GRUB_EHCI_ST_ERROR_INT (1<<1)
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#define GRUB_EHCI_ST_PORT_CHG (1<<2)
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#define GRUB_EHCI_ST_FL_ROLLOVR (1<<3)
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#define GRUB_EHCI_ST_HS_ERROR (1<<4)
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#define GRUB_EHCI_ST_AS_ADVANCE (1<<5)
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#define GRUB_EHCI_ST_HC_HALTED (1<<12)
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#define GRUB_EHCI_ST_RECLAM (1<<13)
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#define GRUB_EHCI_ST_PS_STATUS (1<<14)
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#define GRUB_EHCI_ST_AS_STATUS (1<<15)
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enum
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{
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GRUB_EHCI_ST_INTERRUPT = (1 << 0),
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GRUB_EHCI_ST_ERROR_INT = (1 << 1),
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GRUB_EHCI_ST_PORT_CHG = (1 << 2),
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GRUB_EHCI_ST_FL_ROLLOVR = (1 << 3),
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GRUB_EHCI_ST_HS_ERROR = (1 << 4),
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GRUB_EHCI_ST_AS_ADVANCE = (1 << 5),
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GRUB_EHCI_ST_HC_HALTED = (1 << 12),
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GRUB_EHCI_ST_RECLAM = (1 << 13),
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GRUB_EHCI_ST_PS_STATUS = (1 << 14),
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GRUB_EHCI_ST_AS_STATUS = (1 << 15)
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};
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/* Operational register PORT_STAT_CMD bits */
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#define GRUB_EHCI_PORT_CONNECT (1<<0)
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#define GRUB_EHCI_PORT_CONNECT_CH (1<<1)
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#define GRUB_EHCI_PORT_ENABLED (1<<2)
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#define GRUB_EHCI_PORT_ENABLED_CH (1<<3)
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#define GRUB_EHCI_PORT_OVERCUR (1<<4)
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#define GRUB_EHCI_PORT_OVERCUR_CH (1<<5)
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#define GRUB_EHCI_PORT_RESUME (1<<6)
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#define GRUB_EHCI_PORT_SUSPEND (1<<7)
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#define GRUB_EHCI_PORT_RESET (1<<8)
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#define GRUB_EHCI_PORT_LINE_STAT (3<<10)
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#define GRUB_EHCI_PORT_POWER (1<<12)
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#define GRUB_EHCI_PORT_OWNER (1<<13)
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#define GRUB_EHCI_PORT_INDICATOR (3<<14)
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#define GRUB_EHCI_PORT_TEST (0xf<<16)
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#define GRUB_EHCI_PORT_WON_CONN_E (1<<20)
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#define GRUB_EHCI_PORT_WON_DISC_E (1<<21)
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#define GRUB_EHCI_PORT_WON_OVER_E (1<<22)
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enum
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{
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GRUB_EHCI_PORT_CONNECT = (1<<0),
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GRUB_EHCI_PORT_CONNECT_CH = (1<<1),
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GRUB_EHCI_PORT_ENABLED = (1<<2),
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GRUB_EHCI_PORT_ENABLED_CH = (1<<3),
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GRUB_EHCI_PORT_OVERCUR = (1<<4),
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GRUB_EHCI_PORT_OVERCUR_CH = (1<<5),
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GRUB_EHCI_PORT_RESUME = (1<<6),
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GRUB_EHCI_PORT_SUSPEND = (1<<7),
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GRUB_EHCI_PORT_RESET = (1<<8),
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GRUB_EHCI_PORT_LINE_STAT = (3<<10),
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GRUB_EHCI_PORT_POWER = (1<<12),
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GRUB_EHCI_PORT_OWNER = (1<<13),
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GRUB_EHCI_PORT_INDICATOR = (3<<14),
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GRUB_EHCI_PORT_TEST = (0xf<<16),
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GRUB_EHCI_PORT_WON_CONN_E = (1<<20),
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GRUB_EHCI_PORT_WON_DISC_E = (1<<21),
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GRUB_EHCI_PORT_WON_OVER_E = (1<<22),
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#define GRUB_EHCI_PORT_LINE_SE0 (0<<10)
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#define GRUB_EHCI_PORT_LINE_K (1<<10)
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#define GRUB_EHCI_PORT_LINE_J (2<<10)
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#define GRUB_EHCI_PORT_LINE_UNDEF (3<<10)
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#define GRUB_EHCI_PORT_LINE_LOWSP GRUB_EHCI_PORT_LINE_K /* K state means low speed */
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#define GRUB_EHCI_PORT_WMASK ~(GRUB_EHCI_PORT_CONNECT_CH | \
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GRUB_EHCI_PORT_ENABLED_CH | \
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GRUB_EHCI_PORT_OVERCUR_CH)
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GRUB_EHCI_PORT_LINE_SE0 = (0<<10),
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GRUB_EHCI_PORT_LINE_K = (1<<10),
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GRUB_EHCI_PORT_LINE_J = (2<<10),
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GRUB_EHCI_PORT_LINE_UNDEF = (3<<10),
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GRUB_EHCI_PORT_LINE_LOWSP = GRUB_EHCI_PORT_LINE_K, /* K state means low speed */
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GRUB_EHCI_PORT_WMASK = ~(GRUB_EHCI_PORT_CONNECT_CH
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| GRUB_EHCI_PORT_ENABLED_CH
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| GRUB_EHCI_PORT_OVERCUR_CH)
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};
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/* Operational register CONFIGFLAGS bits */
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#define GRUB_EHCI_CF_EHCI_OWNER (1<<0)
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enum
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{
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GRUB_EHCI_CF_EHCI_OWNER = (1<<0)
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};
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/* Queue Head & Transfer Descriptor constants */
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#define GRUB_EHCI_HPTR_OFF 5 /* Horiz. pointer bit offset */
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#define GRUB_EHCI_HPTR_TYPE_MASK (3<<1)
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#define GRUB_EHCI_HPTR_TYPE_ITD (0<<1)
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#define GRUB_EHCI_HPTR_TYPE_QH (1<<1)
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#define GRUB_EHCI_HPTR_TYPE_SITD (2<<1)
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#define GRUB_EHCI_HPTR_TYPE_FSTN (3<<1)
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enum
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{
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GRUB_EHCI_HPTR_TYPE_MASK = (3<<1),
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GRUB_EHCI_HPTR_TYPE_ITD = (0<<1),
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GRUB_EHCI_HPTR_TYPE_QH = (1<<1),
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GRUB_EHCI_HPTR_TYPE_SITD = (2<<1),
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GRUB_EHCI_HPTR_TYPE_FSTN = (3<<1)
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};
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#define GRUB_EHCI_C (1<<27)
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#define GRUB_EHCI_MAXPLEN_MASK (0x7ff<<16)
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#define GRUB_EHCI_MAXPLEN_OFF 16
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#define GRUB_EHCI_H (1<<15)
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#define GRUB_EHCI_DTC (1<<14)
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#define GRUB_EHCI_SPEED_MASK (3<<12)
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#define GRUB_EHCI_SPEED_OFF 12
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#define GRUB_EHCI_SPEED_FULL (0<<12)
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#define GRUB_EHCI_SPEED_LOW (1<<12)
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#define GRUB_EHCI_SPEED_HIGH (2<<12)
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#define GRUB_EHCI_SPEED_RESERVED (3<<12)
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#define GRUB_EHCI_EP_NUM_MASK (0xf<<8)
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#define GRUB_EHCI_EP_NUM_OFF 8
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#define GRUB_EHCI_DEVADDR_MASK 0x7f
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enum
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{
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GRUB_EHCI_C = (1<<27),
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GRUB_EHCI_MAXPLEN_MASK = (0x7ff<<16),
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GRUB_EHCI_H = (1<<15),
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GRUB_EHCI_DTC = (1<<14),
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GRUB_EHCI_SPEED_MASK = (3<<12),
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GRUB_EHCI_SPEED_FULL = (0<<12),
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GRUB_EHCI_SPEED_LOW = (1<<12),
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GRUB_EHCI_SPEED_HIGH = (2<<12),
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GRUB_EHCI_SPEED_RESERVED = (3<<12),
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GRUB_EHCI_EP_NUM_MASK = (0xf<<8),
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GRUB_EHCI_DEVADDR_MASK = 0x7f,
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GRUB_EHCI_TARGET_MASK = (GRUB_EHCI_EP_NUM_MASK
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| GRUB_EHCI_DEVADDR_MASK)
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};
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#define GRUB_EHCI_TARGET_MASK (GRUB_EHCI_EP_NUM_MASK \
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| GRUB_EHCI_DEVADDR_MASK)
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enum
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{
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GRUB_EHCI_MAXPLEN_OFF = 16,
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GRUB_EHCI_SPEED_OFF = 12,
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GRUB_EHCI_EP_NUM_OFF = 8
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};
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#define GRUB_EHCI_MULT_MASK (3<30)
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#define GRUB_EHCI_MULT_OFF 30
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#define GRUB_EHCI_MULT_RESERVED (0<<30)
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#define GRUB_EHCI_MULT_ONE (0<<30)
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#define GRUB_EHCI_MULT_TWO (0<<30)
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#define GRUB_EHCI_MULT_THREE (0<<30)
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#define GRUB_EHCI_DEVPORT_MASK (0x7f<<23)
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#define GRUB_EHCI_DEVPORT_OFF 23
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#define GRUB_EHCI_HUBADDR_MASK (0x7f<<16)
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#define GRUB_EHCI_HUBADDR_OFF 16
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enum
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{
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GRUB_EHCI_MULT_MASK = (3<<30),
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GRUB_EHCI_MULT_RESERVED = (0<<30),
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GRUB_EHCI_MULT_ONE = (0<<30),
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GRUB_EHCI_MULT_TWO = (0<<30),
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GRUB_EHCI_MULT_THREE = (0<<30),
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GRUB_EHCI_DEVPORT_MASK = (0x7f<<23),
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GRUB_EHCI_HUBADDR_MASK = (0x7f<<16)
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};
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enum
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{
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GRUB_EHCI_MULT_OFF = 30,
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GRUB_EHCI_DEVPORT_OFF = 23,
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GRUB_EHCI_HUBADDR_OFF = 16
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};
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#define GRUB_EHCI_TERMINATE (1<<0)
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#define GRUB_EHCI_TOGGLE (1<<31)
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#define GRUB_EHCI_TOTAL_MASK (0x7fff << 16)
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#define GRUB_EHCI_TOTAL_OFF 16
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#define GRUB_EHCI_CERR_MASK (3<<10)
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#define GRUB_EHCI_CERR_OFF 10
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#define GRUB_EHCI_CERR_0 (0<<10)
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#define GRUB_EHCI_CERR_1 (1<<10)
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#define GRUB_EHCI_CERR_2 (2<<10)
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#define GRUB_EHCI_CERR_3 (3<<10)
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#define GRUB_EHCI_PIDCODE_OUT (0<<8)
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#define GRUB_EHCI_PIDCODE_IN (1<<8)
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#define GRUB_EHCI_PIDCODE_SETUP (2<<8)
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#define GRUB_EHCI_STATUS_MASK 0xff
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#define GRUB_EHCI_STATUS_ACTIVE (1<<7)
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#define GRUB_EHCI_STATUS_HALTED (1<<6)
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#define GRUB_EHCI_STATUS_BUFERR (1<<5)
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#define GRUB_EHCI_STATUS_BABBLE (1<<4)
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#define GRUB_EHCI_STATUS_TRANERR (1<<3)
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#define GRUB_EHCI_STATUS_MISSDMF (1<<2)
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#define GRUB_EHCI_STATUS_SPLITST (1<<1)
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#define GRUB_EHCI_STATUS_PINGERR (1<<0)
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enum
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{
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GRUB_EHCI_TOTAL_MASK = (0x7fff << 16),
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GRUB_EHCI_CERR_MASK = (3<<10),
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GRUB_EHCI_CERR_0 = (0<<10),
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GRUB_EHCI_CERR_1 = (1<<10),
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GRUB_EHCI_CERR_2 = (2<<10),
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GRUB_EHCI_CERR_3 = (3<<10),
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GRUB_EHCI_PIDCODE_OUT = (0<<8),
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GRUB_EHCI_PIDCODE_IN = (1<<8),
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GRUB_EHCI_PIDCODE_SETUP = (2<<8),
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GRUB_EHCI_STATUS_MASK = 0xff,
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GRUB_EHCI_STATUS_ACTIVE = (1<<7),
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GRUB_EHCI_STATUS_HALTED = (1<<6),
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GRUB_EHCI_STATUS_BUFERR = (1<<5),
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GRUB_EHCI_STATUS_BABBLE = (1<<4),
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GRUB_EHCI_STATUS_TRANERR = (1<<3),
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GRUB_EHCI_STATUS_MISSDMF = (1<<2),
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GRUB_EHCI_STATUS_SPLITST = (1<<1),
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GRUB_EHCI_STATUS_PINGERR = (1<<0)
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};
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enum
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{
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GRUB_EHCI_TOTAL_OFF = 16,
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GRUB_EHCI_CERR_OFF = 10
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};
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#define GRUB_EHCI_BUFPTR_MASK (0xfffff<<12)
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#define GRUB_EHCI_QHTDPTR_MASK 0xffffffe0
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@ -214,10 +263,6 @@ GRUB_MOD_LICENSE ("GPLv3+");
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#define GRUB_EHCI_BUFPAGELEN 0x1000
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#define GRUB_EHCI_MAXBUFLEN 0x5000
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#define GRUB_EHCI_QHPTR_TO_INDEX (qh) \
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((grub_uint32_t)qh - (grub_uint32_t)e->qh) / \
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sizeof(grub_ehci_qh_t)
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struct grub_ehci_td;
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struct grub_ehci_qh;
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typedef volatile struct grub_ehci_td *grub_ehci_td_t;
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Reference in a new issue