Init DDR2 controller
This commit is contained in:
Vladimir 'phcoder' Serbinenko
parent
7517048135
commit
813a5f2d33
4 changed files with 307 additions and 35 deletions
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@ -22,6 +22,7 @@
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#include <grub/pci.h>
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#include <grub/serial.h>
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#include <grub/cs5536.h>
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#include <grub/smbus.h>
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.set noreorder
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.set noat
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@ -103,21 +104,102 @@ __start:
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sb $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL3) ($t0)
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sb $t1, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL2) ($t0)
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ori $a0, $zero, 0x50
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/* Yeeloong has only one memory slot. */
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/* Output first byte on serial for debugging. */
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ori $a1, $zero, GRUB_SMB_RAM_START_ADDR
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bal read_spd
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move $a1, $zero
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move $a0, $zero
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bal printhex
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move $a0, $v0
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ori $a0, $zero, 0x50
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bal read_spd
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ori $a1, $zero, 2
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ori $a0, $zero, 2
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ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_TYPE_DDR2
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lui $a0, %hi(unimplemented_memory_type)
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bne $t0, $v0, fatal
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addiu $a0, $a0, %hi(unimplemented_memory_type)
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/* And here is our goal: DDR2 controller initialisation. */
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lui $t0, 0xbfe0
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ld $t1, 0x0180($t0)
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andi $t1, $t1, 0x4ff
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sd $t1, 0x0180($t0)
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b continue
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. = start + GRUB_MACHINE_FLASH_TLB_REFILL - GRUB_MACHINE_FLASH_START
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tlb_refill:
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mfc0 $s1, $14
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mfc0 $s2, $8
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move $s3, $ra
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lui $a0, %hi(epc)
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bal message
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addiu $a0, $a0, %lo(epc)
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bal printhex
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move $a0, $v0
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move $a0, $s1
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lui $a0, %hi(badvaddr)
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bal message
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addiu $a0, $a0, %lo(badvaddr)
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bal printhex
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move $a0, $s2
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lui $a0, %hi(return_msg)
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bal message
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addiu $a0, $a0, %lo(return_msg)
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bal printhex
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move $a0, $s3
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lui $a0, %hi(not_implemented)
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lui $a0, %hi(newline)
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bal message
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addiu $a0, $a0, %lo(newline)
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lui $a0, %hi(unhandled_tlb_refill)
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b fatal
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addiu $a0, $a0, %lo(not_implemented)
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addiu $a0, $a0, %lo(unhandled_tlb_refill)
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. = start + GRUB_MACHINE_FLASH_CACHE_ERROR - GRUB_MACHINE_FLASH_START
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cache_error:
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lui $a0, %hi(unhandled_cache_error)
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b fatal
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addiu $a0, $a0, %lo(unhandled_cache_error)
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. = start + GRUB_MACHINE_FLASH_OTHER_EXCEPTION - GRUB_MACHINE_FLASH_START
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other_exception:
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mfc0 $s0, $13
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mfc0 $s1, $14
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mfc0 $s2, $8
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lui $a0, %hi(cause)
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bal message
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addiu $a0, $a0, %lo(cause)
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bal printhex
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move $a0, $s0
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lui $a0, %hi(epc)
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bal message
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addiu $a0, $a0, %lo(epc)
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bal printhex
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move $a0, $s1
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lui $a0, %hi(badvaddr)
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bal message
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addiu $a0, $a0, %lo(badvaddr)
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bal printhex
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move $a0, $s2
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lui $a0, %hi(newline)
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bal message
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addiu $a0, $a0, %lo(newline)
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lui $a0, %hi(unhandled_exception)
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b fatal
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addiu $a0, $a0, %lo(unhandled_exception)
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/* Same as similarly named C function but in asm since
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we need it early. */
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@ -171,7 +253,7 @@ message:
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addiu $a0, $a0, 1
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jr $ra
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nop
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/* Print 32-bit hexadecimal on serial.
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In: $a0. Out: None. Clobbered: $a0, $t0, $t1, $t2
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*/
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@ -202,25 +284,7 @@ fatal:
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self:
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b self
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nop
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. = start + GRUB_MACHINE_FLASH_TLB_REFILL - GRUB_MACHINE_FLASH_START
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tlb_refill:
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lui $a0, %hi(unhandled_tlb_refill)
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b fatal
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addiu $a0, $a0, %lo(unhandled_tlb_refill)
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. = start + GRUB_MACHINE_FLASH_CACHE_ERROR - GRUB_MACHINE_FLASH_START
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cache_error:
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lui $a0, %hi(unhandled_cache_error)
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b fatal
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addiu $a0, $a0, %lo(unhandled_cache_error)
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. = start + GRUB_MACHINE_FLASH_OTHER_EXCEPTION - GRUB_MACHINE_FLASH_START
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other_exception:
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lui $a0, %hi(unhandled_exception)
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b fatal
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addiu $a0, $a0, %lo(unhandled_exception)
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/* Write CS5536 MSR.
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In: $a0 address, $a1 lower word, $a2 upper word.
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Out: None
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@ -251,7 +315,7 @@ return:
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jr $ra
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nop
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/* Read SPD byte. In: $a0 device, $a1 byte. Out: $v0 read byte (0x100 on failure).
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/* Read SPD byte. In: $a0 byte, $a1 device. Out: $v0 read byte (0x100 on failure).
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Clobbered: $t0, $t1, $t2, $t3, $a0. */
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read_spd:
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move $t2, $a0
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@ -268,7 +332,7 @@ read_spd:
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/* Send device address. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
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sll $t1, $t2, 1
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sll $t1, $a1, 1
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bal smbus_wait
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sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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@ -281,7 +345,7 @@ read_spd:
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/* Send byte address. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
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bal smbus_wait
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sb $a1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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sb $t2, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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/* Send START. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_CTRL1 + GRUB_MACHINE_PCI_IO_BASE)
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@ -292,7 +356,7 @@ read_spd:
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/* Send device address. */
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lui $t0, %hi(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE)
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sll $t1, $t2, 1
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sll $t1, $a1, 1
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ori $t1, $t1, 1
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bal smbus_wait
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sb $t1, %lo(GRUB_CS5536_LBAR_SMBUS + GRUB_CS5536_SMB_REG_DATA + GRUB_MACHINE_PCI_IO_BASE) ($t0)
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@ -321,3 +385,156 @@ unhandled_tlb_refill: .asciz "Unhandled TLB refill.\n\r"
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unhandled_cache_error: .asciz "Unhandled cache error.\n\r"
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unhandled_exception: .asciz "Unhandled exception.\n\r"
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smbus_enabled: .asciz "SMBus controller enabled.\n\r"
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unimplemented_memory_type: .asciz "non-DDR2 memory isn't supported.\n\r"
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no_cas_latency: .asciz "Couldn't determine CAS latency.\n\r"
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cause: .asciz "Cause: "
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epc: .asciz "\n\rEPC: "
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badvaddr: .asciz "\n\rBadVaddr: "
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newline: .asciz "\n\r"
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return_msg: .asciz "\n\rReturn address: "
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.p2align 3
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regdump:
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.quad 0x0100010000000101 /* 0 */
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.quad 0x0100010100000000 /* 2 */
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.quad 0x0101000001000000 /* 3 */
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.quad 0x0100020200010101 /* 4 */
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.quad 0x0a04030603050203 /* 6 */
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.quad 0x0f0e040000010a0b /* 7 */
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.quad 0x0000010200000102 /* 8 */
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.quad 0x0000060c00000000 /* 9 */
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.quad 0x2323233f3f1f0200 /* a */
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.quad 0x5f7f232323232323 /* b */
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.quad 0x002a3c0615000000 /* c */
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.quad 0x002a002a002a002a /* d */
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.quad 0x002a002a002a002a /* e */
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.quad 0x00b40020006d0004 /* f */
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.quad 0x070007ff00000087 /* 10 */
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.quad 0x000000000016101f /* 11 */
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.quad 0x001c000000000000 /* 12 */
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.quad 0x28e1000200c8006b /* 13 */
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.quad 0x0000204200c8002f /* 14 */
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.quad 0x0000000000030d40 /* 15 */
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.quad 0 /* 16 */
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.quad 0 /* 17 */
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.quad 0 /* 18 */
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.quad 0 /* 19 */
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.quad 0 /* 1a */
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.quad 0 /* 1b */
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.quad 0 /* 1c */
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.p2align
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write_dumpreg:
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ld $t2, 0($t6)
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sd $t2, 0($t4)
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addiu $t4, $t4, 0x10
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jr $ra
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addiu $t6, $t6, 0x8
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continue:
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lui $t4, %hi(GRUB_MACHINE_DDR2_BASE)
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addiu $t4, $t4, %lo(GRUB_MACHINE_DDR2_BASE)
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lui $t6, %hi(regdump)
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/* 0 */
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bal write_dumpreg
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addiu $t6, $t6, %lo(regdump)
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/* 1 */
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ori $a1, $a1, 0x50
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move $t8, $zero
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lui $t5, 0x0001
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bal read_spd
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ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_BANKS_ADDR
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ori $t7, $zero, 8
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bne $v0, $t7, 1f
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ori $t5, $t5, 0x0001
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ori $t8, $t8, GRUB_MACHINE_DDR2_REG1_HI_8BANKS
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1:
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dsll $t8, $t8, 32
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or $t5, $t5, $t8
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sd $t5, 0 ($t4)
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addiu $t4, $t4, 0x10
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/* 2 */
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bal write_dumpreg
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nop
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/* 3 */
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bal write_dumpreg
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nop
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/* 4 */
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bal write_dumpreg
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nop
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/* 5 */
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/* FIXME: figure termination resistance. */
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ori $t5, $zero, 0x2
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bal read_spd
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ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_ROWS_ADDR
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/* $v0 = 15 - $v0. */
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xori $v0, $v0, 0xf
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andi $v0, $v0, 0x7
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sll $v0, $v0, 8
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or $t5, $t5, $v0
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/* Find the fastest supported CAS latency. */
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bal read_spd
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ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_ADDR
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ori $t0, $zero, GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_MIN_VALUE
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ori $t1, $zero, (1 << GRUB_SMBUS_SPD_MEMORY_CAS_LATENCY_MIN_VALUE)
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2:
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and $t2, $t1, $v0
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bne $t2, $zero, 1f
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ori $t3, $zero, 8
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lui $a0, %hi(no_cas_latency)
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beq $t0, $t3, fatal
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addiu $a0, $a0, %lo(no_cas_latency)
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addiu $t0, $t0, 1
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b 2b
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sll $t1, $t1, 1
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1:
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sll $t0, $t0, 16
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or $t5, $t5, $t0
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bal read_spd
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ori $a0, $zero, GRUB_SMBUS_SPD_MEMORY_NUM_COLUMNS_ADDR
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/* $v0 = 15 - ($v0 + 1) = 14 - $v0. */
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addiu $v0, $v0, 1
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xori $v0, $v0, 0xf
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andi $v0, $v0, 0x7
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sll $v0, 24
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or $t5, $t5, $v0
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sd $t5, 0 ($t4)
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addiu $t4, $t4, 0x10
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ori $t7, $zero, 0x16
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1:
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ld $t2, 0($t6)
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sd $t2, 0($t4)
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addiu $t4, $t4, 0x10
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addiu $t7, $t7, -1
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bne $t7, $zero, 1b
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addiu $t6, $t6, 0x8
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lui $t4, %hi(GRUB_MACHINE_DDR2_BASE)
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ld $t5, (%lo(GRUB_MACHINE_DDR2_BASE) + 0x30) ($t4)
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ori $t0, $zero, 1
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dsll $t0, $t0, 40
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or $t5, $t5, $t0
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sd $t5, (%lo(GRUB_MACHINE_DDR2_BASE) + 0x30) ($t4)
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/* Desactivate DDR2 registers. */
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lui $t0, 0xbfe0
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ld $t1, 0x0180($t0)
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ori $t1, $t1, 0x100
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sd $t1, 0x0180($t0)
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addiu $a0, $zero, -1
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addiu $a1, $zero, -1
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addiu $a2, $zero, -1
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