Dedicated DMA allocation functions. CS5536 OHCI support.
This commit is contained in:
parent
c7c75cf4cb
commit
8b1cf5e87f
13 changed files with 817 additions and 85 deletions
175
bus/usb/ohci.c
175
bus/usb/ohci.c
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@ -24,8 +24,9 @@
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#include <grub/misc.h>
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#include <grub/pci.h>
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#include <grub/cpu/pci.h>
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#include <grub/i386/io.h>
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#include <grub/cpu/io.h>
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#include <grub/time.h>
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#include <grub/cs5536.h>
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struct grub_ohci_hcca
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{
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@ -63,13 +64,15 @@ struct grub_ohci_td
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grub_uint32_t buffer_end;
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} __attribute__((packed));
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typedef struct grub_ohci_td *grub_ohci_td_t;
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typedef struct grub_ohci_ed *grub_ohci_ed_t;
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typedef volatile struct grub_ohci_td *grub_ohci_td_t;
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typedef volatile struct grub_ohci_ed *grub_ohci_ed_t;
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struct grub_ohci
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{
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volatile grub_uint32_t *iobase;
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volatile struct grub_ohci_hcca *hcca;
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grub_uint32_t hcca_addr;
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struct grub_pci_dma_chunk *hcca_chunk;
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struct grub_ohci *next;
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};
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@ -91,10 +94,23 @@ typedef enum
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GRUB_OHCI_REG_BULKCURR,
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GRUB_OHCI_REG_DONEHEAD,
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GRUB_OHCI_REG_FRAME_INTERVAL,
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GRUB_OHCI_REG_PERIODIC_START = 16,
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GRUB_OHCI_REG_RHUBA = 18,
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GRUB_OHCI_REG_RHUBPORT = 21
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} grub_ohci_reg_t;
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#define GRUB_OHCI_RHUB_PORT_POWER_MASK 0x300
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#define GRUB_OHCI_RHUB_PORT_ALL_POWERED 0x200
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#define GRUB_OHCI_REG_FRAME_INTERVAL_FSMPS_MASK 0x8fff0000
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#define GRUB_OHCI_REG_FRAME_INTERVAL_FSMPS_SHIFT 16
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#define GRUB_OHCI_REG_FRAME_INTERVAL_FI_SHIFT 0
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/* XXX: Is this choice of timings sane? */
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#define GRUB_OHCI_FSMPS 0x2778
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#define GRUB_OHCI_PERIODIC_START 0x257f
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#define GRUB_OHCI_FRAME_INTERVAL 0x2edf
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static grub_uint32_t
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grub_ohci_readreg32 (struct grub_ohci *o, grub_ohci_reg_t reg)
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{
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@ -114,51 +130,81 @@ grub_ohci_writereg32 (struct grub_ohci *o,
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controller. If this is the case, initialize it. */
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static int NESTED_FUNC_ATTR
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grub_ohci_pci_iter (grub_pci_device_t dev,
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grub_pci_id_t pciid __attribute__((unused)))
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grub_pci_id_t pciid)
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{
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grub_uint32_t class_code;
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grub_uint32_t class;
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grub_uint32_t subclass;
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grub_uint32_t interf;
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grub_uint32_t base;
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grub_pci_address_t addr;
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struct grub_ohci *o;
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grub_uint32_t revision;
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grub_uint32_t frame_interval;
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addr = grub_pci_make_address (dev, GRUB_PCI_REG_CLASS);
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class_code = grub_pci_read (addr) >> 8;
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interf = class_code & 0xFF;
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subclass = (class_code >> 8) & 0xFF;
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class = class_code >> 16;
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/* If this is not an OHCI controller, just return. */
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if (class != 0x0c || subclass != 0x03 || interf != 0x10)
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return 0;
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int cs5536;
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/* Determine IO base address. */
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addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0);
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base = grub_pci_read (addr);
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grub_dprintf ("ohci", "pciid = %x\n", pciid);
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if (pciid == GRUB_CS5536_PCIID)
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{
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grub_uint64_t basereg;
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cs5536 = 1;
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basereg = grub_cs5536_read_msr (dev, GRUB_CS5536_MSR_USB_OHCI_BASE);
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if (!(basereg & GRUB_CS5536_MSR_USB_BASE_MEMORY_ENABLE))
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{
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/* Shouldn't happen. */
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grub_dprintf ("ohci", "No OHCI address is assigned\n");
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return 0;
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}
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base = (basereg & GRUB_CS5536_MSR_USB_BASE_ADDR_MASK);
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basereg |= GRUB_CS5536_MSR_USB_BASE_BUS_MASTER;
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basereg &= ~GRUB_CS5536_MSR_USB_BASE_PME_ENABLED;
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basereg &= ~GRUB_CS5536_MSR_USB_BASE_PME_STATUS;
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grub_cs5536_write_msr (dev, GRUB_CS5536_MSR_USB_OHCI_BASE, basereg);
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}
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else
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{
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grub_uint32_t class_code;
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grub_uint32_t class;
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grub_uint32_t subclass;
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addr = grub_pci_make_address (dev, GRUB_PCI_REG_CLASS);
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class_code = grub_pci_read (addr) >> 8;
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interf = class_code & 0xFF;
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subclass = (class_code >> 8) & 0xFF;
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class = class_code >> 16;
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/* If this is not an OHCI controller, just return. */
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if (class != 0x0c || subclass != 0x03 || interf != 0x10)
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return 0;
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addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0);
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base = grub_pci_read (addr);
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#if 0
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/* Stop if there is no IO space base address defined. */
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if (! (base & 1))
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return 0;
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/* Stop if there is no IO space base address defined. */
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if (! (base & 1))
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return 0;
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#endif
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grub_dprintf ("ohci", "class=0x%02x 0x%02x interface 0x%02x\n",
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class, subclass, interf);
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}
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/* Allocate memory for the controller and register it. */
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o = grub_malloc (sizeof (*o));
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if (! o)
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return 1;
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o->iobase = (grub_uint32_t *) base;
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o->iobase = grub_pci_device_map_range (dev, base, 0x100);
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grub_dprintf ("ohci", "base=%p\n", o->iobase);
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/* Reserve memory for the HCCA. */
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o->hcca = (struct grub_ohci_hcca *) grub_memalign (256, 256);
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grub_dprintf ("ohci", "class=0x%02x 0x%02x interface 0x%02x base=%p\n",
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class, subclass, interf, o->iobase);
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o->hcca_chunk = grub_memalign_dma32 (256, 256);
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if (! o->hcca_chunk)
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return 1;
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o->hcca = grub_dma_get_virt (o->hcca_chunk);
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o->hcca_addr = grub_dma_get_phys (o->hcca_chunk);
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/* Check if the OHCI revision is actually 1.0 as supported. */
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revision = grub_ohci_readreg32 (o, GRUB_OHCI_REG_REVISION);
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if ((revision & 0xFF) != 0x10)
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goto fail;
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/* Backup the frame interval register. */
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frame_interval = grub_ohci_readreg32 (o, GRUB_OHCI_REG_FRAME_INTERVAL);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_RHUBA,
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(grub_ohci_readreg32 (o, GRUB_OHCI_REG_RHUBA)
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& ~GRUB_OHCI_RHUB_PORT_POWER_MASK)
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| GRUB_OHCI_RHUB_PORT_ALL_POWERED);
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/* Suspend the OHCI by issuing a reset. */
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_CMDSTATUS, 1); /* XXX: Magic. */
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grub_millisleep (1);
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grub_dprintf ("ohci", "OHCI reset\n");
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/* Restore the frame interval register. */
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_FRAME_INTERVAL, frame_interval);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_FRAME_INTERVAL,
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(GRUB_OHCI_FSMPS
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<< GRUB_OHCI_REG_FRAME_INTERVAL_FSMPS_SHIFT)
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| (GRUB_OHCI_FRAME_INTERVAL
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<< GRUB_OHCI_REG_FRAME_INTERVAL_FI_SHIFT));
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_PERIODIC_START,
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GRUB_OHCI_PERIODIC_START);
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/* Setup the HCCA. */
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_HCCA, (grub_uint32_t) o->hcca);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_HCCA, o->hcca_addr);
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grub_dprintf ("ohci", "OHCI HCCA\n");
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/* Enable the OHCI. */
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return 0;
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fail:
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#ifndef GRUB_MACHINE_MIPS_YEELOONG
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if (o)
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grub_free ((void *) o->hcca);
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#endif
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grub_free (o);
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return 1;
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return 0;
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}
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@ -229,7 +285,7 @@ grub_ohci_iterate (int (*hook) (grub_usb_controller_t dev))
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static void
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grub_ohci_transaction (grub_ohci_td_t td,
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grub_transfer_type_t type, unsigned int toggle,
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grub_size_t size, char *data)
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grub_size_t size, grub_uint32_t data)
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{
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grub_uint32_t token;
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grub_uint32_t buffer;
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token |= toggle << 24;
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token |= 1 << 25;
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buffer = (grub_uint32_t) data;
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buffer = data;
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buffer_end = buffer + size - 1;
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td->token = grub_cpu_to_le32 (token);
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{
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struct grub_ohci *o = (struct grub_ohci *) dev->data;
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grub_ohci_ed_t ed;
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grub_uint32_t ed_addr;
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struct grub_pci_dma_chunk *ed_chunk, *td_list_chunk;
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grub_ohci_td_t td_list;
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grub_uint32_t td_list_addr;
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grub_uint32_t target;
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grub_uint32_t td_tail;
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grub_uint32_t td_head;
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int i;
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/* Allocate an Endpoint Descriptor. */
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ed = grub_memalign (16, sizeof (*ed));
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if (! ed)
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ed_chunk = grub_memalign_dma32 (256, sizeof (*ed));
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if (! ed_chunk)
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return GRUB_USB_ERR_INTERNAL;
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ed = grub_dma_get_virt (ed_chunk);
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ed_addr = grub_dma_get_phys (ed_chunk);
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td_list = grub_memalign (16, sizeof (*td_list) * (transfer->transcnt + 1));
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if (! td_list)
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td_list_chunk = grub_memalign_dma32 (256, sizeof (*td_list)
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* (transfer->transcnt + 1));
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if (! td_list_chunk)
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{
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grub_free ((void *) ed);
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grub_dma_free (ed_chunk);
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return GRUB_USB_ERR_INTERNAL;
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}
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td_list = grub_dma_get_virt (td_list_chunk);
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td_list_addr = grub_dma_get_phys (td_list_chunk);
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grub_dprintf ("ohci", "alloc=%p\n", td_list);
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grub_dprintf ("ohci", "alloc=%p/0x%x\n", td_list, td_list_addr);
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/* Setup all Transfer Descriptors. */
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for (i = 0; i < transfer->transcnt; i++)
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grub_ohci_transaction (&td_list[i], tr->pid, tr->toggle,
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tr->size, tr->data);
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td_list[i].next_td = grub_cpu_to_le32 (&td_list[i + 1]);
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td_list[i].next_td = grub_cpu_to_le32 (td_list_addr
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+ (i + 1) * sizeof (td_list[0]));
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}
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/* Setup the Endpoint Descriptor. */
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/* Set the maximum packet size. */
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target |= transfer->max << 16;
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td_head = (grub_uint32_t) td_list;
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td_head = td_list_addr;
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td_tail = (grub_uint32_t) &td_list[transfer->transcnt];
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td_tail = td_list_addr + transfer->transcnt * sizeof (*td_list);
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ed->target = grub_cpu_to_le32 (target);
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ed->td_head = grub_cpu_to_le32 (td_head);
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status &= ~(1 << 2);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_CMDSTATUS, status);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_BULKHEAD, (grub_uint32_t) ed);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_BULKHEAD, ed_addr);
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/* Enable the Bulk list. */
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control |= 1 << 5;
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status &= ~(1 << 1);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_CMDSTATUS, status);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_CONTROLHEAD,
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(grub_uint32_t) ed);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_CONTROLHEAD, ed_addr);
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_CONTROLHEAD+1,
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(grub_uint32_t) ed);
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ed_addr);
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/* Enable the Control list. */
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control |= 1 << 4;
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{
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grub_uint8_t errcode;
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grub_ohci_td_t tderr;
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grub_uint32_t td_err_addr;
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tderr = (grub_ohci_td_t) grub_ohci_readreg32 (o,
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GRUB_OHCI_REG_DONEHEAD);
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td_err_addr = grub_ohci_readreg32 (o, GRUB_OHCI_REG_DONEHEAD);
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tderr = (grub_ohci_td_t) ((char *) td_list
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+ (td_err_addr - td_list_addr));
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errcode = tderr->token >> 28;
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switch (errcode)
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grub_ohci_writereg32 (o, GRUB_OHCI_REG_CMDSTATUS, status);
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/* XXX */
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grub_free (td_list);
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grub_free (ed);
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grub_dma_free (td_list_chunk);
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grub_dma_free (ed_chunk);
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return err;
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}
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