Enable caches on yeeloong
This commit is contained in:
Vladimir 'phcoder' Serbinenko
parent
32f86589a6
commit
bf8b8ab725
2 changed files with 132 additions and 0 deletions
57
include/grub/mips/loongson.h
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57
include/grub/mips/loongson.h
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@ -0,0 +1,57 @@
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/*
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* GRUB -- GRand Unified Bootloader
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* Copyright (C) 2010 Free Software Foundation, Inc.
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*
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* GRUB is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GRUB is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef GRUB_LOONGSON_CPU_HEADER
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#define GRUB_LOONGSON_CPU_HEADER 1
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#define GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG $16
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#define GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_ILINESIZE 0x10
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#define GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_DLINESIZE 0x8
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#define GRUB_CPU_LOONGSON_COP0_CACHE_DSIZE_SHIFT 6
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#define GRUB_CPU_LOONGSON_COP0_CACHE_ISIZE_SHIFT 9
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#define GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK 0x7
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#define GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET 12
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#define GRUB_CPU_LOONGSON_COP0_I_INDEX_INVALIDATE 0
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#define GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE 9
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#define GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE 11
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#define GRUB_CPU_LOONGSON_COP0_I_INDEX_BIT_OFFSET 5
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#define GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET 5
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#define GRUB_CPU_LOONGSON_COP0_S_INDEX_BIT_OFFSET 5
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#define GRUB_CPU_LOONGSON_CACHE_ACCELERATED 7
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#define GRUB_CPU_LOONGSON_CACHE_UNCACHED 2
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#define GRUB_CPU_LOONGSON_CACHE_CACHED 3
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#define GRUB_CPU_LOONGSON_CACHE_TYPE_MASK 7
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#define GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_SMALL 4
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#define GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG 5
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#define GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_SMALL 16
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#define GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_BIG 32
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#define GRUB_CPU_LOONGSON_I_CACHE_LOG_WAYS 2
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#define GRUB_CPU_LOONGSON_D_CACHE_LOG_WAYS 2
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#define GRUB_CPU_LOONGSON_S_CACHE_LOG_WAYS 2
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/* Fixme: determine dynamically. */
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#define GRUB_CPU_LOONGSON_SECONDARY_CACHE_LOG_SIZE 19
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#define GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO $28
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#define GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI $29
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#endif
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@ -19,6 +19,7 @@
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#include <grub/mips/yeeloong/serial.h>
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#include <grub/mips/yeeloong/pci.h>
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#include <grub/mips/yeeloong/boot.h>
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#include <grub/mips/loongson.h>
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#include <grub/pci.h>
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#include <grub/serial.h>
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#include <grub/cs5536.h>
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@ -392,6 +393,7 @@ epc: .asciz "\n\rEPC: "
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badvaddr: .asciz "\n\rBadVaddr: "
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newline: .asciz "\n\r"
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return_msg: .asciz "\n\rReturn address: "
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caches_enabled: .asciz "Caches enabled\n\r"
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.p2align 3
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@ -535,6 +537,79 @@ continue:
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ori $t1, $t1, 0x100
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sd $t1, 0x0180($t0)
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/* Enable cache. */
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mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
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addiu $t1, $zero, ~GRUB_CPU_LOONGSON_CACHE_TYPE_MASK
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and $t0, $t1, $t1
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/* Set line size to 32 bytes and disabled cache. */
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ori $t0, $t0, (GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_ILINESIZE \
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| GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG_DLINESIZE \
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| GRUB_CPU_LOONGSON_CACHE_ACCELERATED)
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mtc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
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/* Invalidate all I-cache entries. */
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srl $t1, $t0, GRUB_CPU_LOONGSON_COP0_CACHE_ISIZE_SHIFT
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andi $t1, $t1, GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK
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ori $t2, $zero, (1 << (GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET \
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- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
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- GRUB_CPU_LOONGSON_I_CACHE_LOG_WAYS))
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sll $t1, $t2, $t1
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lui $t2, 0x8000
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1:
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cache GRUB_CPU_LOONGSON_COP0_I_INDEX_INVALIDATE, 0($t2)
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addiu $t1, $t1, -1
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bne $t1, $zero, 1b
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addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_I_INDEX_BIT_OFFSET)
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/* Invalidate all D-cache entries. */
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srl $t1, $t0, GRUB_CPU_LOONGSON_COP0_CACHE_DSIZE_SHIFT
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andi $t1, $t1, GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_MASK
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ori $t2, $zero, (1 << (GRUB_CPU_LOONGSON_COP0_CACHE_SIZE_OFFSET \
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- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
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- GRUB_CPU_LOONGSON_D_CACHE_LOG_WAYS))
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sll $t1, $t2, $t1
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lui $t2, 0x8000
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mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO
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mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI
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1:
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/* All four ways. */
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cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 0($t2)
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cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 1($t2)
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cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 2($t2)
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cache GRUB_CPU_LOONGSON_COP0_D_INDEX_TAG_STORE, 3($t2)
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addiu $t1, $t1, -1
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bne $t1, $zero, 1b
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addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET)
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/* Invalidate all S-cache entries. */
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ori $t1, $zero, (1 << (GRUB_CPU_LOONGSON_SECONDARY_CACHE_LOG_SIZE \
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- GRUB_CPU_LOONGSON_CACHE_LINE_SIZE_LOG_BIG \
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- GRUB_CPU_LOONGSON_S_CACHE_LOG_WAYS))
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lui $t2, 0x8000
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mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGLO
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mtc0 $zero, GRUB_CPU_LOONGSON_COP0_CACHE_TAGHI
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1:
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/* All four ways. */
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cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 0($t2)
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cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 1($t2)
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cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 2($t2)
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cache GRUB_CPU_LOONGSON_COP0_S_INDEX_TAG_STORE, 3($t2)
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addiu $t1, $t1, -1
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bne $t1, $zero, 1b
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addiu $t2, $t2, (1 << GRUB_CPU_LOONGSON_COP0_D_INDEX_BIT_OFFSET)
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/* Finally enable cache. */
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mfc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
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addiu $t1, $zero, ~GRUB_CPU_LOONGSON_CACHE_TYPE_MASK
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and $t0, $t1, $t1
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ori $t0, $t0, GRUB_CPU_LOONGSON_CACHE_CACHED
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mtc0 $t0, GRUB_CPU_LOONGSON_COP0_CACHE_CONFIG
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lui $a0, %hi(caches_enabled)
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bal message
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addiu $a0, $a0, %lo(caches_enabled)
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addiu $a0, $zero, -1
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addiu $a1, $zero, -1
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addiu $a2, $zero, -1
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