Init video early on yeeloong to avoid being rebooted by watchdog.
* grub-core/Makefile.am (gensm712): New target. (sm712_start.S): Likewise. (boot/mips/loongson/fwstart.S): Depend on sm712_start.S * grub-core/boot/mips/loongson/fwstart.S [!FULOONG2F]: Init SM712. * grub-core/video/sm712.c [GENINIT]: Generate compact init procedure description. * include/grub/vga.h: Move registry definitions to... * include/grub/vgaregs.h: ... here.
This commit is contained in:
Vladimir 'phcoder' Serbinenko
parent
5f92c8a110
commit
c50c867da3
6 changed files with 507 additions and 288 deletions
13
ChangeLog
13
ChangeLog
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@ -1,3 +1,16 @@
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2012-06-26 Vladimir Serbinenko <phcoder@gmail.com>
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Init video early on yeeloong to avoid being rebooted by watchdog.
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* grub-core/Makefile.am (gensm712): New target.
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(sm712_start.S): Likewise.
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(boot/mips/loongson/fwstart.S): Depend on sm712_start.S
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* grub-core/boot/mips/loongson/fwstart.S [!FULOONG2F]: Init SM712.
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* grub-core/video/sm712.c [GENINIT]: Generate compact init procedure
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description.
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* include/grub/vga.h: Move registry definitions to...
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* include/grub/vgaregs.h: ... here.
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2012-06-26 Vladimir Serbinenko <phcoder@gmail.com>
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* grub-core/boot/decompressor/minilib.c (grub_memcmp): Fix the compare
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@ -40,6 +40,15 @@ trigtables.c: gentrigtables gentrigtables.c $(top_srcdir)/configure.ac
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$(builddir)/gentrigtables > $@
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CLEANFILES += trigtables.c
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gensm712: video/sm712.c
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$(BUILD_CC) -DGENINIT -o $@ -I$(top_builddir) -I$(top_builddir)/include -I$(top_srcdir)/include $(CPPFLAGS) $<
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CLEANFILES += gensm712
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# trigtables.c
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sm712_start.S: gensm712 video/sm712.c $(top_srcdir)/configure.ac
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$(builddir)/gensm712 > $@
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CLEANFILES += sm712_start.S
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# XXX Use Automake's LEX & YACC support
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grub_script.tab.h: script/parser.y
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$(YACC) -d -p grub_script_yy -b grub_script $<
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@ -55,6 +64,7 @@ rs_decoder.S: $(srcdir)/lib/reed_solomon.c
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$(TARGET_CC) $(TARGET_CPPFLAGS) $(TARGET_CFLAGS) -Os -I$(top_builddir) -S -DSTANDALONE -o $@ $< -g0 -mregparm=3 -ffreestanding
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kern/i386/pc/startup.S: $(builddir)/rs_decoder.S
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boot/mips/loongson/fwstart.S: $(builddir)/sm712_start.S
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CLEANFILES += grub_script.yy.c grub_script.yy.h
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@ -26,6 +26,12 @@
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#include <grub/cs5536.h>
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#include <grub/smbus.h>
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#ifndef FULOONG2F
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#include <grub/vgaregs.h>
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#define GRUB_SM712_REG_BASE 0x700000
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#define GRUB_SM712_PCIID 0x0712126f
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#endif
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#ifdef FULOONG2F
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#define GRUB_MACHINE_SERIAL_PORT GRUB_MACHINE_SERIAL_PORT2
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#define GRUB_MACHINE_SERIAL_DIVISOR_115200 GRUB_MACHINE_SERIAL_PORT2_DIVISOR_115200
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@ -748,3 +754,140 @@ continue:
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#endif
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cached_continue:
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#ifndef FULOONG2F
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/* We have to init video early enough or watchdog will reboot us. */
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/* Setup PCI controller. */
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lui $t0, %hi (GRUB_CPU_LOONGSON_PCI_HIT1_SEL_LO)
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lui $t1, %hi(0x8000000c)
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addiu $t1, $t1, %lo(0x8000000c)
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sw $t1, %lo (GRUB_CPU_LOONGSON_PCI_HIT1_SEL_LO) ($t0)
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li $t1, 0xffffffff
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sw $t1, %lo (GRUB_CPU_LOONGSON_PCI_HIT1_SEL_HI) ($t0)
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li $t0, GRUB_MACHINE_PCI_CONTROLLER_HEADER
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li $t1, (GRUB_PCI_COMMAND_PARITY_ERROR | GRUB_PCI_COMMAND_BUS_MASTER \
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| GRUB_PCI_COMMAND_MEM_ENABLED)
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sh $t0, GRUB_PCI_REG_COMMAND ($t1)
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li $t1, ((1 << GRUB_PCI_STATUS_DEVSEL_TIMING_SHIFT) \
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| GRUB_PCI_STATUS_FAST_B2B_CAPABLE \
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| GRUB_PCI_STATUS_66MHZ_CAPABLE \
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| GRUB_PCI_STATUS_CAPABILITIES)
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sh $t0, GRUB_PCI_REG_STATUS ($t1)
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li $t0, 0xff
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sw $t0, GRUB_PCI_REG_CACHELINE ($t1)
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lui $t1, %hi(0x80000000 | GRUB_PCI_ADDR_MEM_TYPE_64 \
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| GRUB_PCI_ADDR_MEM_PREFETCH)
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addiu $t1, $t1, %lo(0x80000000 | GRUB_PCI_ADDR_MEM_TYPE_64 \
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| GRUB_PCI_ADDR_MEM_PREFETCH)
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sw $t0, GRUB_PCI_REG_ADDRESS_REG0 ($t1)
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sw $zero, GRUB_PCI_REG_ADDRESS_REG1 ($t1)
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/* Find video. */
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/* $t4 chooses device in priority encoding. */
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/* Resulting value is kept in GRUB_MACHINE_PCI_CONF_CTRL_REG.
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This way we don't need to sacrifice a register for it. */
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retry_sm712:
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/* We have only one bus (0). Function is 0. */
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lui $t0, %hi(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR)
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lui $t1, %hi(GRUB_MACHINE_PCI_CONFSPACE)
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lui $t3, %hi(GRUB_SM712_PCIID)
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addiu $t3, $t3, %lo(GRUB_SM712_PCIID)
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ori $t4, $zero, 1
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1:
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andi $t4, $t4, ((1 << GRUB_PCI_NUM_DEVICES) - 1)
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/* In case of failure try again. SM712 may be slow to come up. */
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beql $t4, $zero, retry_sm712
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nop
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sw $t4, %lo(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR) ($t0)
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lw $t2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_PCI_REG_PCI_ID) ($t1)
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bnel $t2, $t3, 1b
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sll $t4, $t4, 1
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/* FIXME: choose address dynamically if needed. */
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#define SM712_MAP 0x04000000
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lui $t2, %hi(SM712_MAP)
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sw $t4, %lo(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR) ($t0)
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sw $t2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_PCI_REG_ADDRESS_REG0) ($t1)
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/* Set latency. */
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li $t2, 0x8
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sw $t4, %lo(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR) ($t0)
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sw $t2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_PCI_REG_CACHELINE) ($t1)
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/* Enable address spaces. */
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li $t2, 0x7
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sw $t4, %lo(GRUB_MACHINE_PCI_CONF_CTRL_REG_ADDR) ($t0)
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sw $t2, (%lo(GRUB_MACHINE_PCI_CONFSPACE) + GRUB_PCI_REG_COMMAND) ($t1)
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lui $t3, %hi(GRUB_MACHINE_PCI_IO_BASE + GRUB_VGA_IO_SR_INDEX)
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li $t2, 0x18
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sb $t2, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_VGA_IO_SR_INDEX)($t3)
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lui $t3, %hi(GRUB_MACHINE_PCI_IO_BASE + GRUB_VGA_IO_SR_DATA)
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li $t2, 0x11
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sb $t2, %lo(GRUB_MACHINE_PCI_IO_BASE + GRUB_VGA_IO_SR_DATA)($t3)
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li $t2, ((((SM712_MAP & ~GRUB_MACHINE_PCI_WIN_OFFSET_MASK) \
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>> GRUB_MACHINE_PCI_WIN_SHIFT) \
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& GRUB_MACHINE_PCI_WIN_MASK))
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lui $t3, %hi(0xbfe00110)
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addiu $t3, $t3, %lo(0xbfe00110)
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sw $t2, 0 ($t3)
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li $t2, (GRUB_MACHINE_PCI_WIN1_ADDR \
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| (SM712_MAP & GRUB_MACHINE_PCI_WIN_OFFSET_MASK))
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lui $t3, %hi(GRUB_SM712_REG_BASE)
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addiu $t3, $t3, %lo(GRUB_SM712_REG_BASE)
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addu $t2, $t2, $t3
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lui $t0, %hi(init_table - 0x20000000)
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addiu $t0, $t0, %lo(init_table - 0x20000000)
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lui $t1, %hi(init_table_end - 0x20000000)
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addiu $t1, $t1, %lo(init_table_end - 0x20000000)
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li $t5, 0x80
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addiu $t6, $t2, 0x3c0
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table_cont:
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lb $t3, 0($t0)
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andi $t5, $t3, 0x80
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andi $t3, $t3, 0x7f
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addu $t3, $t3, $t6
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lb $t4, 1($t0)
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bne $zero, $t5, 1f
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addiu $t0, $t0, 2
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b 2f
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sb $t4, 0($t3)
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1:
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lb $t4, 0($t3)
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2:
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bne $t0, $t1, table_cont
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nop
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lui $t3, %hi(0x40c000 - GRUB_SM712_REG_BASE)
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addiu $t3, $t3, %lo(0x40c000 - GRUB_SM712_REG_BASE)
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addu $t1, $t2, $t3
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sw $zero, 0xc ($t1)
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sw $zero, 0x40 ($t1)
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li $t3, 0x20000
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sw $t3, 0x0 ($t1)
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lui $t3, %hi(0x1020100)
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addiu $t3, $t3, %lo(0x1020100)
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sw $t3, 0x10 ($t1)
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li $t4, 0x16
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sb $t4, GRUB_VGA_IO_SR_INDEX($t2)
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lb $t4, GRUB_VGA_IO_SR_DATA($t2)
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b init_end
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nop
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init_table:
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#include "sm712_start.S"
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init_table_end:
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.align 4
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init_end:
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#endif
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@ -18,6 +18,7 @@
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#define grub_video_render_target grub_video_fbrender_target
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#if !defined (TEST) && !defined(GENINIT)
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#include <grub/err.h>
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#include <grub/types.h>
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#include <grub/dl.h>
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@ -28,6 +29,15 @@
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#include <grub/pci.h>
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#include <grub/vga.h>
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#include <grub/cache.h>
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#else
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typedef unsigned char grub_uint8_t;
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typedef unsigned short grub_uint16_t;
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typedef unsigned int grub_uint32_t;
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typedef int grub_err_t;
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#include <grub/vgaregs.h>
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#include <stdio.h>
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#define ARRAY_SIZE(array) (sizeof (array) / sizeof (array[0]))
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#endif
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#include "sm712_init.c"
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@ -194,16 +204,20 @@ static struct
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static struct
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{
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#if !defined (TEST) && !defined(GENINIT)
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struct grub_video_mode_info mode_info;
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#endif
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volatile grub_uint8_t *ptr;
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grub_uint8_t *cached_ptr;
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int mapped;
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grub_uint32_t base;
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#if !defined (TEST) && !defined(GENINIT)
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grub_pci_device_t dev;
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#endif
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} framebuffer;
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#ifndef TEST
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#if !defined (TEST) && !defined(GENINIT)
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static grub_err_t
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grub_video_sm712_video_init (void)
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{
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@ -232,6 +246,10 @@ grub_sm712_write_reg (grub_uint8_t val, grub_uint16_t addr)
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{
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#ifdef TEST
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printf (" {1, 0x%x, 0x%x},\n", addr, val);
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#elif defined (GENINIT)
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printf (" .byte 0x%02x, 0x%02x\n", (addr - 0x3c0), val);
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if ((addr - 0x3c0) & ~0x7f)
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printf ("FAIL\n");
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#else
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*(volatile grub_uint8_t *) (framebuffer.ptr + GRUB_SM712_REG_BASE
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+ addr) = val;
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@ -243,6 +261,10 @@ grub_sm712_read_reg (grub_uint16_t addr)
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{
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#ifdef TEST
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printf (" {-1, 0x%x, 0x5},\n", addr);
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#elif defined (GENINIT)
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if ((addr - 0x3c0) & ~0x7f)
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printf ("FAIL\n");
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printf (" .byte 0x%04x, 0x00\n", (addr - 0x3c0) | 0x80);
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#else
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return *(volatile grub_uint8_t *) (framebuffer.ptr + GRUB_SM712_REG_BASE
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+ addr);
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@ -342,12 +364,12 @@ static grub_err_t
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grub_video_sm712_setup (unsigned int width, unsigned int height,
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unsigned int mode_type, unsigned int mode_mask __attribute__ ((unused)))
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{
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unsigned i;
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#if !defined (TEST) && !defined(GENINIT)
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int depth;
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grub_err_t err;
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int found = 0;
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unsigned i;
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#ifndef TEST
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auto int NESTED_FUNC_ATTR find_card (grub_pci_device_t dev, grub_pci_id_t pciid __attribute__ ((unused)));
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int NESTED_FUNC_ATTR find_card (grub_pci_device_t dev, grub_pci_id_t pciid __attribute__ ((unused)))
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{
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@ -382,7 +404,6 @@ grub_video_sm712_setup (unsigned int width, unsigned int height,
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grub_pci_iterate (find_card);
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if (!found)
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return grub_error (GRUB_ERR_IO, "Couldn't find graphics card");
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#endif
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/* Fill mode info details. */
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framebuffer.mode_info.width = 1024;
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framebuffer.mode_info.height = 600;
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@ -401,12 +422,11 @@ grub_video_sm712_setup (unsigned int width, unsigned int height,
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framebuffer.mode_info.blue_field_pos = 0;
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framebuffer.mode_info.reserved_mask_size = 0;
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framebuffer.mode_info.reserved_field_pos = 0;
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#ifndef TEST
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framebuffer.mode_info.blit_format
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= grub_video_get_blit_format (&framebuffer.mode_info);
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#endif
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#ifndef TEST
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#if !defined (TEST) && !defined(GENINIT)
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if (found && framebuffer.base == 0)
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{
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grub_pci_address_t addr;
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@ -427,7 +447,7 @@ grub_video_sm712_setup (unsigned int width, unsigned int height,
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#endif
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/* We can safely discard volatile attribute. */
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#ifndef TEST
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#if !defined (TEST) && !defined(GENINIT)
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framebuffer.ptr
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= grub_pci_device_map_range (framebuffer.dev,
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framebuffer.base,
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|
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@ -440,12 +460,12 @@ grub_video_sm712_setup (unsigned int width, unsigned int height,
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framebuffer.mapped = 1;
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/* Initialise SM712. */
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#ifndef TEST
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#if !defined (TEST) && !defined(GENINIT)
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/* FIXME */
|
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grub_vga_sr_write (0x11, 0x18);
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#endif
|
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|
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#ifndef TEST
|
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#if !defined (TEST) && !defined(GENINIT)
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/* Prevent garbage from appearing on the screen. */
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grub_memset ((void *) framebuffer.cached_ptr, 0,
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framebuffer.mode_info.height * framebuffer.mode_info.pitch);
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|
|
@ -687,7 +707,7 @@ grub_video_sm712_setup (unsigned int width, unsigned int height,
|
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| GRUB_VGA_IO_MISC_COLOR,
|
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GRUB_VGA_IO_MISC_WRITE);
|
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|
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#ifndef TEST
|
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#if !defined (TEST) && !defined(GENINIT)
|
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/* Undocumented? */
|
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*(volatile grub_uint32_t *) ((char *) framebuffer.ptr + 0x40c00c) = 0;
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*(volatile grub_uint32_t *) ((char *) framebuffer.ptr + 0x40c040) = 0;
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|
|
@ -697,7 +717,7 @@ grub_video_sm712_setup (unsigned int width, unsigned int height,
|
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|
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(void) grub_sm712_sr_read (0x16);
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#ifndef TEST
|
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#if !defined (TEST) && !defined(GENINIT)
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err = grub_video_fb_setup (mode_type, mode_mask,
|
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&framebuffer.mode_info,
|
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framebuffer.cached_ptr, NULL, NULL);
|
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|
|
@ -707,11 +727,13 @@ grub_video_sm712_setup (unsigned int width, unsigned int height,
|
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/* Copy default palette to initialize emulated palette. */
|
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err = grub_video_fb_set_palette (0, GRUB_VIDEO_FBSTD_NUMCOLORS,
|
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grub_video_fbstd_colors);
|
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#endif
|
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return err;
|
||||
#else
|
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return 0;
|
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#endif
|
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}
|
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|
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#ifndef TEST
|
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#if !defined (TEST) && !defined(GENINIT)
|
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|
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static grub_err_t
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grub_video_sm712_swap_buffers (void)
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|
|
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|
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@ -26,208 +26,7 @@
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#define GRUB_MACHINE_PCI_IO_BASE 0xb4000000
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#endif
|
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|
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enum
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{
|
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GRUB_VGA_IO_ARX = 0x3c0,
|
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GRUB_VGA_IO_ARX_READ = 0x3c1,
|
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GRUB_VGA_IO_MISC_WRITE = 0x3c2,
|
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GRUB_VGA_IO_SR_INDEX = 0x3c4,
|
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GRUB_VGA_IO_SR_DATA = 0x3c5,
|
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GRUB_VGA_IO_PIXEL_MASK = 0x3c6,
|
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GRUB_VGA_IO_PALLETTE_READ_INDEX = 0x3c7,
|
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GRUB_VGA_IO_PALLETTE_WRITE_INDEX = 0x3c8,
|
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GRUB_VGA_IO_PALLETTE_DATA = 0x3c9,
|
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GRUB_VGA_IO_GR_INDEX = 0x3ce,
|
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GRUB_VGA_IO_GR_DATA = 0x3cf,
|
||||
GRUB_VGA_IO_CR_INDEX = 0x3d4,
|
||||
GRUB_VGA_IO_CR_DATA = 0x3d5,
|
||||
GRUB_VGA_IO_INPUT_STATUS1_REGISTER = 0x3da
|
||||
};
|
||||
|
||||
#define GRUB_VGA_IO_INPUT_STATUS1_VERTR_BIT 0x08
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_HTOTAL = 0x00,
|
||||
GRUB_VGA_CR_HORIZ_END = 0x01,
|
||||
GRUB_VGA_CR_HBLANK_START = 0x02,
|
||||
GRUB_VGA_CR_HBLANK_END = 0x03,
|
||||
GRUB_VGA_CR_HORIZ_SYNC_PULSE_START = 0x04,
|
||||
GRUB_VGA_CR_HORIZ_SYNC_PULSE_END = 0x05,
|
||||
GRUB_VGA_CR_VERT_TOTAL = 0x06,
|
||||
GRUB_VGA_CR_OVERFLOW = 0x07,
|
||||
GRUB_VGA_CR_BYTE_PANNING = 0x08,
|
||||
GRUB_VGA_CR_CELL_HEIGHT = 0x09,
|
||||
GRUB_VGA_CR_CURSOR_START = 0x0a,
|
||||
GRUB_VGA_CR_CURSOR_END = 0x0b,
|
||||
GRUB_VGA_CR_START_ADDR_HIGH_REGISTER = 0x0c,
|
||||
GRUB_VGA_CR_START_ADDR_LOW_REGISTER = 0x0d,
|
||||
GRUB_VGA_CR_CURSOR_ADDR_HIGH = 0x0e,
|
||||
GRUB_VGA_CR_CURSOR_ADDR_LOW = 0x0f,
|
||||
GRUB_VGA_CR_VSYNC_START = 0x10,
|
||||
GRUB_VGA_CR_VSYNC_END = 0x11,
|
||||
GRUB_VGA_CR_VDISPLAY_END = 0x12,
|
||||
GRUB_VGA_CR_PITCH = 0x13,
|
||||
GRUB_VGA_CR_UNDERLINE_LOCATION = 0x14,
|
||||
GRUB_VGA_CR_VERTICAL_BLANK_START = 0x15,
|
||||
GRUB_VGA_CR_VERTICAL_BLANK_END = 0x16,
|
||||
GRUB_VGA_CR_MODE = 0x17,
|
||||
GRUB_VGA_CR_LINE_COMPARE = 0x18,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_BYTE_PANNING_NORMAL = 0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_UNDERLINE_LOCATION_DWORD_MODE = 0x40
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_IO_MISC_COLOR = 0x01,
|
||||
GRUB_VGA_IO_MISC_ENABLE_VRAM_ACCESS = 0x02,
|
||||
GRUB_VGA_IO_MISC_28MHZ = 0x04,
|
||||
GRUB_VGA_IO_MISC_EXTERNAL_CLOCK_0 = 0x08,
|
||||
GRUB_VGA_IO_MISC_UPPER_64K = 0x20,
|
||||
GRUB_VGA_IO_MISC_NEGATIVE_HORIZ_POLARITY = 0x40,
|
||||
GRUB_VGA_IO_MISC_NEGATIVE_VERT_POLARITY = 0x80,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_ARX_MODE = 0x10,
|
||||
GRUB_VGA_ARX_OVERSCAN = 0x11,
|
||||
GRUB_VGA_ARX_COLOR_PLANE_ENABLE = 0x12,
|
||||
GRUB_VGA_ARX_HORIZONTAL_PANNING = 0x13,
|
||||
GRUB_VGA_ARX_COLOR_SELECT = 0x14
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_ARX_MODE_TEXT = 0x00,
|
||||
GRUB_VGA_ARX_MODE_GRAPHICS = 0x01,
|
||||
GRUB_VGA_ARX_MODE_ENABLE_256COLOR = 0x40
|
||||
};
|
||||
|
||||
#define GRUB_VGA_CR_WIDTH_DIVISOR 8
|
||||
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT 7
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK 0x02
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT 3
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK 0x40
|
||||
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT 8
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_TOTAL1_MASK 0x01
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT 4
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_TOTAL2_MASK 0x20
|
||||
|
||||
#define GRUB_VGA_CR_OVERFLOW_VSYNC_START1_SHIFT 6
|
||||
#define GRUB_VGA_CR_OVERFLOW_VSYNC_START1_MASK 0x04
|
||||
#define GRUB_VGA_CR_OVERFLOW_VSYNC_START2_SHIFT 2
|
||||
#define GRUB_VGA_CR_OVERFLOW_VSYNC_START2_MASK 0x80
|
||||
|
||||
#define GRUB_VGA_CR_OVERFLOW_HEIGHT1_SHIFT 7
|
||||
#define GRUB_VGA_CR_OVERFLOW_HEIGHT1_MASK 0x02
|
||||
#define GRUB_VGA_CR_OVERFLOW_HEIGHT2_SHIFT 3
|
||||
#define GRUB_VGA_CR_OVERFLOW_HEIGHT2_MASK 0xc0
|
||||
#define GRUB_VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT 4
|
||||
#define GRUB_VGA_CR_OVERFLOW_LINE_COMPARE_MASK 0x10
|
||||
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK 0x40
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT 3
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK 0x20
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT 4
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_DOUBLE_SCAN 0x80
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_CURSOR_START_DISABLE = (1 << 5)
|
||||
};
|
||||
|
||||
#define GRUB_VGA_CR_PITCH_DIVISOR 8
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_MODE_NO_CGA = 0x01,
|
||||
GRUB_VGA_CR_MODE_NO_HERCULES = 0x02,
|
||||
GRUB_VGA_CR_MODE_ADDRESS_WRAP = 0x20,
|
||||
GRUB_VGA_CR_MODE_BYTE_MODE = 0x40,
|
||||
GRUB_VGA_CR_MODE_TIMING_ENABLE = 0x80
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_SR_RESET = 0,
|
||||
GRUB_VGA_SR_CLOCKING_MODE = 1,
|
||||
GRUB_VGA_SR_MAP_MASK_REGISTER = 2,
|
||||
GRUB_VGA_SR_CHAR_MAP_SELECT = 3,
|
||||
GRUB_VGA_SR_MEMORY_MODE = 4,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_SR_RESET_ASYNC = 1,
|
||||
GRUB_VGA_SR_RESET_SYNC = 2
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_SR_CLOCKING_MODE_8_DOT_CLOCK = 1
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_SR_MEMORY_MODE_NORMAL = 0,
|
||||
GRUB_VGA_SR_MEMORY_MODE_EXTERNAL_VIDEO_MEMORY = 2,
|
||||
GRUB_VGA_SR_MEMORY_MODE_SEQUENTIAL_ADDRESSING = 4,
|
||||
GRUB_VGA_SR_MEMORY_MODE_CHAIN4 = 8,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_GR_SET_RESET_PLANE = 0,
|
||||
GRUB_VGA_GR_SET_RESET_PLANE_ENABLE = 1,
|
||||
GRUB_VGA_GR_COLOR_COMPARE = 2,
|
||||
GRUB_VGA_GR_DATA_ROTATE = 3,
|
||||
GRUB_VGA_GR_READ_MAP_REGISTER = 4,
|
||||
GRUB_VGA_GR_MODE = 5,
|
||||
GRUB_VGA_GR_GR6 = 6,
|
||||
GRUB_VGA_GR_COLOR_COMPARE_DISABLE = 7,
|
||||
GRUB_VGA_GR_BITMASK = 8,
|
||||
GRUB_VGA_GR_MAX
|
||||
};
|
||||
|
||||
#define GRUB_VGA_ALL_PLANES 0xf
|
||||
#define GRUB_VGA_NO_PLANES 0x0
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_GR_DATA_ROTATE_NOP = 0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_TEXT_TEXT_PLANE = 0,
|
||||
GRUB_VGA_TEXT_ATTR_PLANE = 1,
|
||||
GRUB_VGA_TEXT_FONT_PLANE = 2
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_GR_GR6_GRAPHICS_MODE = 1,
|
||||
GRUB_VGA_GR_GR6_MMAP_A0 = (1 << 2),
|
||||
GRUB_VGA_GR_GR6_MMAP_CGA = (3 << 2)
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_GR_MODE_READ_MODE1 = 0x08,
|
||||
GRUB_VGA_GR_MODE_ODD_EVEN = 0x10,
|
||||
GRUB_VGA_GR_MODE_ODD_EVEN_SHIFT = 0x20,
|
||||
GRUB_VGA_GR_MODE_256_COLOR = 0x40
|
||||
};
|
||||
#include <grub/vgaregs.h>
|
||||
|
||||
static inline void
|
||||
grub_vga_gr_write (grub_uint8_t val, grub_uint8_t addr)
|
||||
|
|
@ -313,77 +112,4 @@ grub_vga_read_arx (grub_uint8_t addr)
|
|||
return val;
|
||||
}
|
||||
|
||||
struct grub_video_hw_config
|
||||
{
|
||||
unsigned vertical_total;
|
||||
unsigned vertical_blank_start;
|
||||
unsigned vertical_blank_end;
|
||||
unsigned vertical_sync_start;
|
||||
unsigned vertical_sync_end;
|
||||
unsigned line_compare;
|
||||
unsigned vdisplay_end;
|
||||
unsigned pitch;
|
||||
unsigned horizontal_total;
|
||||
unsigned horizontal_blank_start;
|
||||
unsigned horizontal_blank_end;
|
||||
unsigned horizontal_sync_pulse_start;
|
||||
unsigned horizontal_sync_pulse_end;
|
||||
unsigned horizontal_end;
|
||||
};
|
||||
|
||||
static inline void
|
||||
grub_vga_set_geometry (struct grub_video_hw_config *config,
|
||||
void (*cr_write) (grub_uint8_t val, grub_uint8_t addr))
|
||||
{
|
||||
unsigned vertical_total = config->vertical_total - 2;
|
||||
unsigned vertical_blank_start = config->vertical_blank_start - 1;
|
||||
unsigned vdisplay_end = config->vdisplay_end - 1;
|
||||
grub_uint8_t overflow, cell_height_reg;
|
||||
|
||||
/* Disable CR0-7 write protection. */
|
||||
cr_write (0, GRUB_VGA_CR_VSYNC_END);
|
||||
|
||||
overflow = ((vertical_total >> GRUB_VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VERT_TOTAL1_MASK)
|
||||
| ((vertical_total >> GRUB_VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VERT_TOTAL2_MASK)
|
||||
| ((config->vertical_sync_start >> GRUB_VGA_CR_OVERFLOW_VSYNC_START2_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VSYNC_START2_MASK)
|
||||
| ((config->vertical_sync_start >> GRUB_VGA_CR_OVERFLOW_VSYNC_START1_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VSYNC_START1_MASK)
|
||||
| ((vdisplay_end >> GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK)
|
||||
| ((vdisplay_end >> GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK)
|
||||
| ((config->vertical_sync_start >> GRUB_VGA_CR_OVERFLOW_VSYNC_START1_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VSYNC_START1_MASK)
|
||||
| ((config->line_compare >> GRUB_VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_LINE_COMPARE_MASK);
|
||||
|
||||
cell_height_reg = ((vertical_blank_start
|
||||
>> GRUB_VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT)
|
||||
& GRUB_VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK)
|
||||
| ((config->line_compare >> GRUB_VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT)
|
||||
& GRUB_VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK);
|
||||
|
||||
cr_write (config->horizontal_total - 1, GRUB_VGA_CR_HTOTAL);
|
||||
cr_write (config->horizontal_end - 1, GRUB_VGA_CR_HORIZ_END);
|
||||
cr_write (config->horizontal_blank_start - 1, GRUB_VGA_CR_HBLANK_START);
|
||||
cr_write (config->horizontal_blank_end, GRUB_VGA_CR_HBLANK_END);
|
||||
cr_write (config->horizontal_sync_pulse_start,
|
||||
GRUB_VGA_CR_HORIZ_SYNC_PULSE_START);
|
||||
cr_write (config->horizontal_sync_pulse_end,
|
||||
GRUB_VGA_CR_HORIZ_SYNC_PULSE_END);
|
||||
cr_write (vertical_total & 0xff, GRUB_VGA_CR_VERT_TOTAL);
|
||||
cr_write (overflow, GRUB_VGA_CR_OVERFLOW);
|
||||
cr_write (cell_height_reg, GRUB_VGA_CR_CELL_HEIGHT);
|
||||
cr_write (config->vertical_sync_start & 0xff, GRUB_VGA_CR_VSYNC_START);
|
||||
cr_write (config->vertical_sync_end & 0x0f, GRUB_VGA_CR_VSYNC_END);
|
||||
cr_write (vdisplay_end & 0xff, GRUB_VGA_CR_VDISPLAY_END);
|
||||
cr_write (config->pitch & 0xff, GRUB_VGA_CR_PITCH);
|
||||
cr_write (vertical_blank_start & 0xff, GRUB_VGA_CR_VERTICAL_BLANK_START);
|
||||
cr_write (config->vertical_blank_end & 0xff, GRUB_VGA_CR_VERTICAL_BLANK_END);
|
||||
cr_write (config->line_compare & 0xff, GRUB_VGA_CR_LINE_COMPARE);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
305
include/grub/vgaregs.h
Normal file
305
include/grub/vgaregs.h
Normal file
|
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
* GRUB -- GRand Unified Bootloader
|
||||
* Copyright (C) 2010 Free Software Foundation, Inc.
|
||||
*
|
||||
* GRUB is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* GRUB is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef GRUB_VGAREGS_HEADER
|
||||
#define GRUB_VGAREGS_HEADER 1
|
||||
|
||||
#ifdef ASM_FILE
|
||||
#define GRUB_VGA_IO_SR_INDEX 0x3c4
|
||||
#define GRUB_VGA_IO_SR_DATA 0x3c5
|
||||
#else
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_IO_ARX = 0x3c0,
|
||||
GRUB_VGA_IO_ARX_READ = 0x3c1,
|
||||
GRUB_VGA_IO_MISC_WRITE = 0x3c2,
|
||||
GRUB_VGA_IO_SR_INDEX = 0x3c4,
|
||||
GRUB_VGA_IO_SR_DATA = 0x3c5,
|
||||
GRUB_VGA_IO_PIXEL_MASK = 0x3c6,
|
||||
GRUB_VGA_IO_PALLETTE_READ_INDEX = 0x3c7,
|
||||
GRUB_VGA_IO_PALLETTE_WRITE_INDEX = 0x3c8,
|
||||
GRUB_VGA_IO_PALLETTE_DATA = 0x3c9,
|
||||
GRUB_VGA_IO_GR_INDEX = 0x3ce,
|
||||
GRUB_VGA_IO_GR_DATA = 0x3cf,
|
||||
GRUB_VGA_IO_CR_INDEX = 0x3d4,
|
||||
GRUB_VGA_IO_CR_DATA = 0x3d5,
|
||||
GRUB_VGA_IO_INPUT_STATUS1_REGISTER = 0x3da
|
||||
};
|
||||
|
||||
#define GRUB_VGA_IO_INPUT_STATUS1_VERTR_BIT 0x08
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_HTOTAL = 0x00,
|
||||
GRUB_VGA_CR_HORIZ_END = 0x01,
|
||||
GRUB_VGA_CR_HBLANK_START = 0x02,
|
||||
GRUB_VGA_CR_HBLANK_END = 0x03,
|
||||
GRUB_VGA_CR_HORIZ_SYNC_PULSE_START = 0x04,
|
||||
GRUB_VGA_CR_HORIZ_SYNC_PULSE_END = 0x05,
|
||||
GRUB_VGA_CR_VERT_TOTAL = 0x06,
|
||||
GRUB_VGA_CR_OVERFLOW = 0x07,
|
||||
GRUB_VGA_CR_BYTE_PANNING = 0x08,
|
||||
GRUB_VGA_CR_CELL_HEIGHT = 0x09,
|
||||
GRUB_VGA_CR_CURSOR_START = 0x0a,
|
||||
GRUB_VGA_CR_CURSOR_END = 0x0b,
|
||||
GRUB_VGA_CR_START_ADDR_HIGH_REGISTER = 0x0c,
|
||||
GRUB_VGA_CR_START_ADDR_LOW_REGISTER = 0x0d,
|
||||
GRUB_VGA_CR_CURSOR_ADDR_HIGH = 0x0e,
|
||||
GRUB_VGA_CR_CURSOR_ADDR_LOW = 0x0f,
|
||||
GRUB_VGA_CR_VSYNC_START = 0x10,
|
||||
GRUB_VGA_CR_VSYNC_END = 0x11,
|
||||
GRUB_VGA_CR_VDISPLAY_END = 0x12,
|
||||
GRUB_VGA_CR_PITCH = 0x13,
|
||||
GRUB_VGA_CR_UNDERLINE_LOCATION = 0x14,
|
||||
GRUB_VGA_CR_VERTICAL_BLANK_START = 0x15,
|
||||
GRUB_VGA_CR_VERTICAL_BLANK_END = 0x16,
|
||||
GRUB_VGA_CR_MODE = 0x17,
|
||||
GRUB_VGA_CR_LINE_COMPARE = 0x18,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_BYTE_PANNING_NORMAL = 0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_UNDERLINE_LOCATION_DWORD_MODE = 0x40
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_IO_MISC_COLOR = 0x01,
|
||||
GRUB_VGA_IO_MISC_ENABLE_VRAM_ACCESS = 0x02,
|
||||
GRUB_VGA_IO_MISC_28MHZ = 0x04,
|
||||
GRUB_VGA_IO_MISC_EXTERNAL_CLOCK_0 = 0x08,
|
||||
GRUB_VGA_IO_MISC_UPPER_64K = 0x20,
|
||||
GRUB_VGA_IO_MISC_NEGATIVE_HORIZ_POLARITY = 0x40,
|
||||
GRUB_VGA_IO_MISC_NEGATIVE_VERT_POLARITY = 0x80,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_ARX_MODE = 0x10,
|
||||
GRUB_VGA_ARX_OVERSCAN = 0x11,
|
||||
GRUB_VGA_ARX_COLOR_PLANE_ENABLE = 0x12,
|
||||
GRUB_VGA_ARX_HORIZONTAL_PANNING = 0x13,
|
||||
GRUB_VGA_ARX_COLOR_SELECT = 0x14
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_ARX_MODE_TEXT = 0x00,
|
||||
GRUB_VGA_ARX_MODE_GRAPHICS = 0x01,
|
||||
GRUB_VGA_ARX_MODE_ENABLE_256COLOR = 0x40
|
||||
};
|
||||
|
||||
#define GRUB_VGA_CR_WIDTH_DIVISOR 8
|
||||
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT 7
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK 0x02
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT 3
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK 0x40
|
||||
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT 8
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_TOTAL1_MASK 0x01
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT 4
|
||||
#define GRUB_VGA_CR_OVERFLOW_VERT_TOTAL2_MASK 0x20
|
||||
|
||||
#define GRUB_VGA_CR_OVERFLOW_VSYNC_START1_SHIFT 6
|
||||
#define GRUB_VGA_CR_OVERFLOW_VSYNC_START1_MASK 0x04
|
||||
#define GRUB_VGA_CR_OVERFLOW_VSYNC_START2_SHIFT 2
|
||||
#define GRUB_VGA_CR_OVERFLOW_VSYNC_START2_MASK 0x80
|
||||
|
||||
#define GRUB_VGA_CR_OVERFLOW_HEIGHT1_SHIFT 7
|
||||
#define GRUB_VGA_CR_OVERFLOW_HEIGHT1_MASK 0x02
|
||||
#define GRUB_VGA_CR_OVERFLOW_HEIGHT2_SHIFT 3
|
||||
#define GRUB_VGA_CR_OVERFLOW_HEIGHT2_MASK 0xc0
|
||||
#define GRUB_VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT 4
|
||||
#define GRUB_VGA_CR_OVERFLOW_LINE_COMPARE_MASK 0x10
|
||||
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK 0x40
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT 3
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK 0x20
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT 4
|
||||
#define GRUB_VGA_CR_CELL_HEIGHT_DOUBLE_SCAN 0x80
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_CURSOR_START_DISABLE = (1 << 5)
|
||||
};
|
||||
|
||||
#define GRUB_VGA_CR_PITCH_DIVISOR 8
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_CR_MODE_NO_CGA = 0x01,
|
||||
GRUB_VGA_CR_MODE_NO_HERCULES = 0x02,
|
||||
GRUB_VGA_CR_MODE_ADDRESS_WRAP = 0x20,
|
||||
GRUB_VGA_CR_MODE_BYTE_MODE = 0x40,
|
||||
GRUB_VGA_CR_MODE_TIMING_ENABLE = 0x80
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_SR_RESET = 0,
|
||||
GRUB_VGA_SR_CLOCKING_MODE = 1,
|
||||
GRUB_VGA_SR_MAP_MASK_REGISTER = 2,
|
||||
GRUB_VGA_SR_CHAR_MAP_SELECT = 3,
|
||||
GRUB_VGA_SR_MEMORY_MODE = 4,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_SR_RESET_ASYNC = 1,
|
||||
GRUB_VGA_SR_RESET_SYNC = 2
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_SR_CLOCKING_MODE_8_DOT_CLOCK = 1
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_SR_MEMORY_MODE_NORMAL = 0,
|
||||
GRUB_VGA_SR_MEMORY_MODE_EXTERNAL_VIDEO_MEMORY = 2,
|
||||
GRUB_VGA_SR_MEMORY_MODE_SEQUENTIAL_ADDRESSING = 4,
|
||||
GRUB_VGA_SR_MEMORY_MODE_CHAIN4 = 8,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_GR_SET_RESET_PLANE = 0,
|
||||
GRUB_VGA_GR_SET_RESET_PLANE_ENABLE = 1,
|
||||
GRUB_VGA_GR_COLOR_COMPARE = 2,
|
||||
GRUB_VGA_GR_DATA_ROTATE = 3,
|
||||
GRUB_VGA_GR_READ_MAP_REGISTER = 4,
|
||||
GRUB_VGA_GR_MODE = 5,
|
||||
GRUB_VGA_GR_GR6 = 6,
|
||||
GRUB_VGA_GR_COLOR_COMPARE_DISABLE = 7,
|
||||
GRUB_VGA_GR_BITMASK = 8,
|
||||
GRUB_VGA_GR_MAX
|
||||
};
|
||||
|
||||
#define GRUB_VGA_ALL_PLANES 0xf
|
||||
#define GRUB_VGA_NO_PLANES 0x0
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_GR_DATA_ROTATE_NOP = 0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_TEXT_TEXT_PLANE = 0,
|
||||
GRUB_VGA_TEXT_ATTR_PLANE = 1,
|
||||
GRUB_VGA_TEXT_FONT_PLANE = 2
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_GR_GR6_GRAPHICS_MODE = 1,
|
||||
GRUB_VGA_GR_GR6_MMAP_A0 = (1 << 2),
|
||||
GRUB_VGA_GR_GR6_MMAP_CGA = (3 << 2)
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
GRUB_VGA_GR_MODE_READ_MODE1 = 0x08,
|
||||
GRUB_VGA_GR_MODE_ODD_EVEN = 0x10,
|
||||
GRUB_VGA_GR_MODE_ODD_EVEN_SHIFT = 0x20,
|
||||
GRUB_VGA_GR_MODE_256_COLOR = 0x40
|
||||
};
|
||||
|
||||
struct grub_video_hw_config
|
||||
{
|
||||
unsigned vertical_total;
|
||||
unsigned vertical_blank_start;
|
||||
unsigned vertical_blank_end;
|
||||
unsigned vertical_sync_start;
|
||||
unsigned vertical_sync_end;
|
||||
unsigned line_compare;
|
||||
unsigned vdisplay_end;
|
||||
unsigned pitch;
|
||||
unsigned horizontal_total;
|
||||
unsigned horizontal_blank_start;
|
||||
unsigned horizontal_blank_end;
|
||||
unsigned horizontal_sync_pulse_start;
|
||||
unsigned horizontal_sync_pulse_end;
|
||||
unsigned horizontal_end;
|
||||
};
|
||||
|
||||
static inline void
|
||||
grub_vga_set_geometry (struct grub_video_hw_config *config,
|
||||
void (*cr_write) (grub_uint8_t val, grub_uint8_t addr))
|
||||
{
|
||||
unsigned vertical_total = config->vertical_total - 2;
|
||||
unsigned vertical_blank_start = config->vertical_blank_start - 1;
|
||||
unsigned vdisplay_end = config->vdisplay_end - 1;
|
||||
grub_uint8_t overflow, cell_height_reg;
|
||||
|
||||
/* Disable CR0-7 write protection. */
|
||||
cr_write (0, GRUB_VGA_CR_VSYNC_END);
|
||||
|
||||
overflow = ((vertical_total >> GRUB_VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VERT_TOTAL1_MASK)
|
||||
| ((vertical_total >> GRUB_VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VERT_TOTAL2_MASK)
|
||||
| ((config->vertical_sync_start >> GRUB_VGA_CR_OVERFLOW_VSYNC_START2_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VSYNC_START2_MASK)
|
||||
| ((config->vertical_sync_start >> GRUB_VGA_CR_OVERFLOW_VSYNC_START1_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VSYNC_START1_MASK)
|
||||
| ((vdisplay_end >> GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK)
|
||||
| ((vdisplay_end >> GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK)
|
||||
| ((config->vertical_sync_start >> GRUB_VGA_CR_OVERFLOW_VSYNC_START1_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_VSYNC_START1_MASK)
|
||||
| ((config->line_compare >> GRUB_VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT)
|
||||
& GRUB_VGA_CR_OVERFLOW_LINE_COMPARE_MASK);
|
||||
|
||||
cell_height_reg = ((vertical_blank_start
|
||||
>> GRUB_VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT)
|
||||
& GRUB_VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK)
|
||||
| ((config->line_compare >> GRUB_VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT)
|
||||
& GRUB_VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK);
|
||||
|
||||
cr_write (config->horizontal_total - 1, GRUB_VGA_CR_HTOTAL);
|
||||
cr_write (config->horizontal_end - 1, GRUB_VGA_CR_HORIZ_END);
|
||||
cr_write (config->horizontal_blank_start - 1, GRUB_VGA_CR_HBLANK_START);
|
||||
cr_write (config->horizontal_blank_end, GRUB_VGA_CR_HBLANK_END);
|
||||
cr_write (config->horizontal_sync_pulse_start,
|
||||
GRUB_VGA_CR_HORIZ_SYNC_PULSE_START);
|
||||
cr_write (config->horizontal_sync_pulse_end,
|
||||
GRUB_VGA_CR_HORIZ_SYNC_PULSE_END);
|
||||
cr_write (vertical_total & 0xff, GRUB_VGA_CR_VERT_TOTAL);
|
||||
cr_write (overflow, GRUB_VGA_CR_OVERFLOW);
|
||||
cr_write (cell_height_reg, GRUB_VGA_CR_CELL_HEIGHT);
|
||||
cr_write (config->vertical_sync_start & 0xff, GRUB_VGA_CR_VSYNC_START);
|
||||
cr_write (config->vertical_sync_end & 0x0f, GRUB_VGA_CR_VSYNC_END);
|
||||
cr_write (vdisplay_end & 0xff, GRUB_VGA_CR_VDISPLAY_END);
|
||||
cr_write (config->pitch & 0xff, GRUB_VGA_CR_PITCH);
|
||||
cr_write (vertical_blank_start & 0xff, GRUB_VGA_CR_VERTICAL_BLANK_START);
|
||||
cr_write (config->vertical_blank_end & 0xff, GRUB_VGA_CR_VERTICAL_BLANK_END);
|
||||
cr_write (config->line_compare & 0xff, GRUB_VGA_CR_LINE_COMPARE);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue