53 lines
1.8 KiB
Text
53 lines
1.8 KiB
Text
This directory contains mpn functions optimized for DEC Alpha processors.
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RELEVANT OPTIMIZATION ISSUES
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EV4
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1. This chip has very limited store bandwidth. The on-chip L1 cache is
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write-through, and a cache line is transfered from the store buffer to the
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off-chip L2 in as much 15 cycles on most systems. This delay hurts
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mpn_add_n, mpn_sub_n, mpn_lshift, and mpn_rshift.
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2. Pairing is possible between memory instructions and integer arithmetic
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instructions.
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3. mulq and umulh is documented to have a latency of 23 cycles, but 2 of
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these cycles are pipelined. Thus, multiply instructions can be issued at a
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rate of one each 21nd cycle.
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EV5
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1. The memory bandwidth of this chip seems excellent, both for loads and
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stores. Even when the working set is larger than the on-chip L1 and L2
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caches, the perfromance remain almost unaffected.
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2. mulq has a measured latency of 13 cycles and an issue rate of 1 each 8th
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cycle. umulh has a measured latency of 15 cycles and an issue rate of 1
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each 10th cycle. But the exact timing is somewhat confusing.
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3. mpn_add_n. With 4-fold unrolling, we need 37 instructions, whereof 12
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are memory operations. This will take at least
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ceil(37/2) [dual issue] + 1 [taken branch] = 20 cycles
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We have 12 memory cycles, plus 4 after-store conflict cycles, or 16 data
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cache cycles, which should be completely hidden in the 20 issue cycles.
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The computation is inherently serial, with these dependencies:
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addq
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/ \
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addq cmpult
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cmpult |
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\ /
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or
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I.e., there is a 4 cycle path for each limb, making 16 cycles the absolute
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minimum. We could replace the `or' with a cmoveq/cmovne, which would save
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a cycle on EV5, but that might waste a cycle on EV4. Also, cmov takes 2
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cycles.
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addq
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/ \
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addq cmpult
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cmpult -> cmovne
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STATUS
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