131 lines
2.8 KiB
ArmAsm
131 lines
2.8 KiB
ArmAsm
/*
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* GRUB -- GRand Unified Bootloader
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* Copyright (C) 2013 Free Software Foundation, Inc.
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*
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* GRUB is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* GRUB is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GRUB. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <grub/symbol.h>
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.file "cache.S"
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.text
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.syntax unified
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.arm
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#if !defined (ARMV6) && !defined (ARMV7)
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# error Unsupported architecture version!
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#endif
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.align 2
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/*
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* Simple cache maintenance functions
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*/
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@ r0 - *beg (inclusive)
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@ r1 - *end (exclusive)
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clean_dcache_range:
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@ Clean data cache for range to point-of-unification
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ldr r2, ADDR(EXT_C(grub_arch_cache_dlinesz))
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ldr r2, [r2]
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sub r3, r2, #1 @ align "beg" to start of line
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mvn r3, r3
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and r0, r0, r3
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1: cmp r0, r1
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bge 2f
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#ifdef ARMV6
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mcr p15, 0, r0, c7, c10, 1 @ Clean data cache line by MVA
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#else
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mcr p15, 0, r0, c7, c11, 1 @ DCCMVAU
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#endif
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add r0, r0, r2 @ Next line
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b 1b
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2: DSB
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bx lr
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@ r0 - *beg (inclusive)
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@ r1 - *end (exclusive)
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invalidate_icache_range:
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@ Invalidate instruction cache for range to point-of-unification
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ldr r2, ADDR(EXT_C(grub_arch_cache_ilinesz))
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ldr r2, [r2]
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sub r3, r2, #1 @ align "beg" to start of line
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mvn r3, r3
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and r0, r0, r3
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1: cmp r0, r1
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bge 2f
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mcr p15, 0, r0, c7, c5, 1 @ ICIMVAU
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add r0, r0, r2 @ Next line
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b 1b
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@ Branch predictor invalidate all
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2: mcr p15, 0, r0, c7, c5, 6 @ BPIALL
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DSB
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ISB
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bx lr
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@void grub_arch_sync_caches (void *address, grub_size_t len)
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#ifdef ARMV6
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FUNCTION(grub_arch_sync_caches_armv6)
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#else
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FUNCTION(grub_arch_sync_caches_armv7)
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#endif
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DSB
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add r1, r0, r1
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push {r0-r2, lr}
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bl clean_dcache_range
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pop {r0, r1}
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bl invalidate_icache_range
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pop {r2, pc}
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#ifdef ARMV6
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FUNCTION(grub_arm_disable_caches_mmu_armv6)
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#else
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FUNCTION(grub_arm_disable_caches_mmu_armv7)
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#endif
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push {r4, lr}
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@ disable D-cache
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 2)
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mcr p15, 0, r0, c1, c0, 0
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DSB
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ISB
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@ clean/invalidate D-cache
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bl clean_invalidate_dcache
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@ disable I-cache
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 12)
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mcr p15, 0, r0, c1, c0, 0
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DSB
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ISB
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@ invalidate I-cache (also invalidates branch predictors)
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mcr p15, 0, r0, c7, c5, 0
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DSB
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ISB
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@ clear SCTLR M bit
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 0)
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLB
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mcr p15, 0, r0, c7, c5, 6 @ invalidate branch predictor
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DSB
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ISB
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pop {r4, pc}
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