285 lines
9.7 KiB
C
285 lines
9.7 KiB
C
/*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Copyright (c) 2007, Keir Fraser
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*/
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#ifndef __XEN_PUBLIC_HVM_PARAMS_H__
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#define __XEN_PUBLIC_HVM_PARAMS_H__
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#include "hvm_op.h"
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/*
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* Parameter space for HVMOP_{set,get}_param.
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*/
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#define HVM_PARAM_CALLBACK_IRQ 0
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#define HVM_PARAM_CALLBACK_IRQ_TYPE_MASK xen_mk_ullong(0xFF00000000000000)
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/*
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* How should CPU0 event-channel notifications be delivered?
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*
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* If val == 0 then CPU0 event-channel notifications are not delivered.
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* If val != 0, val[63:56] encodes the type, as follows:
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*/
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#define HVM_PARAM_CALLBACK_TYPE_GSI 0
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/*
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* val[55:0] is a delivery GSI. GSI 0 cannot be used, as it aliases val == 0,
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* and disables all notifications.
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*/
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#define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1
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/*
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* val[55:0] is a delivery PCI INTx line:
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* Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0]
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#define HVM_PARAM_CALLBACK_TYPE_VECTOR 2
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/*
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* val[7:0] is a vector number. Check for XENFEAT_hvm_callback_vector to know
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* if this delivery method is available.
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*/
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#elif defined(__arm__) || defined(__aarch64__)
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#define HVM_PARAM_CALLBACK_TYPE_PPI 2
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/*
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* val[55:16] needs to be zero.
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* val[15:8] is interrupt flag of the PPI used by event-channel:
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* bit 8: the PPI is edge(1) or level(0) triggered
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* bit 9: the PPI is active low(1) or high(0)
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* val[7:0] is a PPI number used by event-channel.
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* This is only used by ARM/ARM64 and masking/eoi the interrupt associated to
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* the notification is handled by the interrupt controller.
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*/
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#define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK 0xFF00
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#define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL 2
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#endif
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/*
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* These are not used by Xen. They are here for convenience of HVM-guest
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* xenbus implementations.
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*/
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#define HVM_PARAM_STORE_PFN 1
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#define HVM_PARAM_STORE_EVTCHN 2
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#define HVM_PARAM_PAE_ENABLED 4
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#define HVM_PARAM_IOREQ_PFN 5
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#define HVM_PARAM_BUFIOREQ_PFN 6
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#define HVM_PARAM_BUFIOREQ_EVTCHN 26
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#if defined(__i386__) || defined(__x86_64__)
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/*
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* Viridian enlightenments
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*
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* (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hypervisor%20Top%20Level%20Functional%20Specification%20v4.0.docx)
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*
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* To expose viridian enlightenments to the guest set this parameter
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* to the desired feature mask. The base feature set must be present
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* in any valid feature mask.
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*/
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#define HVM_PARAM_VIRIDIAN 9
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/* Base+Freq viridian feature sets:
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*
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* - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
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* - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
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* - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX)
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* - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
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* HV_X64_MSR_APIC_FREQUENCY)
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*/
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#define _HVMPV_base_freq 0
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#define HVMPV_base_freq (1 << _HVMPV_base_freq)
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/* Feature set modifications */
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/* Disable timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
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* HV_X64_MSR_APIC_FREQUENCY).
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* This modification restores the viridian feature set to the
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* original 'base' set exposed in releases prior to Xen 4.4.
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*/
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#define _HVMPV_no_freq 1
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#define HVMPV_no_freq (1 << _HVMPV_no_freq)
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/* Enable Partition Time Reference Counter (HV_X64_MSR_TIME_REF_COUNT) */
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#define _HVMPV_time_ref_count 2
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#define HVMPV_time_ref_count (1 << _HVMPV_time_ref_count)
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/* Enable Reference TSC Page (HV_X64_MSR_REFERENCE_TSC) */
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#define _HVMPV_reference_tsc 3
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#define HVMPV_reference_tsc (1 << _HVMPV_reference_tsc)
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/* Use Hypercall for remote TLB flush */
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#define _HVMPV_hcall_remote_tlb_flush 4
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#define HVMPV_hcall_remote_tlb_flush (1 << _HVMPV_hcall_remote_tlb_flush)
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/* Use APIC assist */
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#define _HVMPV_apic_assist 5
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#define HVMPV_apic_assist (1 << _HVMPV_apic_assist)
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/* Enable crash MSRs */
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#define _HVMPV_crash_ctl 6
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#define HVMPV_crash_ctl (1 << _HVMPV_crash_ctl)
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#define HVMPV_feature_mask \
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(HVMPV_base_freq | \
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HVMPV_no_freq | \
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HVMPV_time_ref_count | \
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HVMPV_reference_tsc | \
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HVMPV_hcall_remote_tlb_flush | \
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HVMPV_apic_assist | \
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HVMPV_crash_ctl)
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#endif
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/*
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* Set mode for virtual timers (currently x86 only):
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* delay_for_missed_ticks (default):
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* Do not advance a vcpu's time beyond the correct delivery time for
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* interrupts that have been missed due to preemption. Deliver missed
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* interrupts when the vcpu is rescheduled and advance the vcpu's virtual
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* time stepwise for each one.
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* no_delay_for_missed_ticks:
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* As above, missed interrupts are delivered, but guest time always tracks
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* wallclock (i.e., real) time while doing so.
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* no_missed_ticks_pending:
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* No missed interrupts are held pending. Instead, to ensure ticks are
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* delivered at some non-zero rate, if we detect missed ticks then the
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* internal tick alarm is not disabled if the VCPU is preempted during the
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* next tick period.
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* one_missed_tick_pending:
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* Missed interrupts are collapsed together and delivered as one 'late tick'.
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* Guest time always tracks wallclock (i.e., real) time.
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*/
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#define HVM_PARAM_TIMER_MODE 10
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#define HVMPTM_delay_for_missed_ticks 0
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#define HVMPTM_no_delay_for_missed_ticks 1
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#define HVMPTM_no_missed_ticks_pending 2
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#define HVMPTM_one_missed_tick_pending 3
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/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
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#define HVM_PARAM_HPET_ENABLED 11
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/* Identity-map page directory used by Intel EPT when CR0.PG=0. */
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#define HVM_PARAM_IDENT_PT 12
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/* Device Model domain, defaults to 0. */
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#define HVM_PARAM_DM_DOMAIN 13
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/* ACPI S state: currently support S0 and S3 on x86. */
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#define HVM_PARAM_ACPI_S_STATE 14
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/* TSS used on Intel when CR0.PE=0. */
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#define HVM_PARAM_VM86_TSS 15
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/* Boolean: Enable aligning all periodic vpts to reduce interrupts */
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#define HVM_PARAM_VPT_ALIGN 16
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/* Console debug shared memory ring and event channel */
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#define HVM_PARAM_CONSOLE_PFN 17
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#define HVM_PARAM_CONSOLE_EVTCHN 18
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/*
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* Select location of ACPI PM1a and TMR control blocks. Currently two locations
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* are supported, specified by version 0 or 1 in this parameter:
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* - 0: default, use the old addresses
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* PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48
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* - 1: use the new default qemu addresses
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* PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008
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* You can find these address definitions in <hvm/ioreq.h>
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*/
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#define HVM_PARAM_ACPI_IOPORTS_LOCATION 19
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/* Deprecated */
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#define HVM_PARAM_MEMORY_EVENT_CR0 20
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#define HVM_PARAM_MEMORY_EVENT_CR3 21
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#define HVM_PARAM_MEMORY_EVENT_CR4 22
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#define HVM_PARAM_MEMORY_EVENT_INT3 23
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#define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP 25
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#define HVM_PARAM_MEMORY_EVENT_MSR 30
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/* Boolean: Enable nestedhvm (hvm only) */
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#define HVM_PARAM_NESTEDHVM 24
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/* Params for the mem event rings */
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#define HVM_PARAM_PAGING_RING_PFN 27
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#define HVM_PARAM_MONITOR_RING_PFN 28
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#define HVM_PARAM_SHARING_RING_PFN 29
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/* SHUTDOWN_* action in case of a triple fault */
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#define HVM_PARAM_TRIPLE_FAULT_REASON 31
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#define HVM_PARAM_IOREQ_SERVER_PFN 32
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#define HVM_PARAM_NR_IOREQ_SERVER_PAGES 33
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/* Location of the VM Generation ID in guest physical address space. */
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#define HVM_PARAM_VM_GENERATION_ID_ADDR 34
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/*
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* Set mode for altp2m:
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* disabled: don't activate altp2m (default)
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* mixed: allow access to all altp2m ops for both in-guest and external tools
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* external: allow access to external privileged tools only
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* limited: guest only has limited access (ie. control VMFUNC and #VE)
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*/
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#define HVM_PARAM_ALTP2M 35
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#define XEN_ALTP2M_disabled 0
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#define XEN_ALTP2M_mixed 1
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#define XEN_ALTP2M_external 2
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#define XEN_ALTP2M_limited 3
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/*
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* Size of the x87 FPU FIP/FDP registers that the hypervisor needs to
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* save/restore. This is a workaround for a hardware limitation that
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* does not allow the full FIP/FDP and FCS/FDS to be restored.
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*
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* Valid values are:
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*
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* 8: save/restore 64-bit FIP/FDP and clear FCS/FDS (default if CPU
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* has FPCSDS feature).
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*
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* 4: save/restore 32-bit FIP/FDP, FCS/FDS, and clear upper 32-bits of
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* FIP/FDP.
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*
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* 0: allow hypervisor to choose based on the value of FIP/FDP
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* (default if CPU does not have FPCSDS).
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*
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* If FPCSDS (bit 13 in CPUID leaf 0x7, subleaf 0x0) is set, the CPU
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* never saves FCS/FDS and this parameter should be left at the
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* default of 8.
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*/
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#define HVM_PARAM_X87_FIP_WIDTH 36
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/*
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* TSS (and its size) used on Intel when CR0.PE=0. The address occupies
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* the low 32 bits, while the size is in the high 32 ones.
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*/
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#define HVM_PARAM_VM86_TSS_SIZED 37
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/* Enable MCA capabilities. */
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#define HVM_PARAM_MCA_CAP 38
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#define XEN_HVM_MCA_CAP_LMCE (xen_mk_ullong(1) << 0)
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#define XEN_HVM_MCA_CAP_MASK XEN_HVM_MCA_CAP_LMCE
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#define HVM_NR_PARAMS 39
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#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
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